Design Rule Check Report
------------------------

Report Written : 29.06.2009 13:51:23
Design Path    : H:\ProjPCB\ADAC\FPGA\FPGA-CORERAM.pcb
Design Title   : 
Created        : 28.04.2008 12:48:28
Last Saved     : 29.06.2009 11:51:08
Editing Time   : 1098 min
Units          : thou (precision 2)

Settings
--------

Spacings

    Tracks                        Yes
    Pads and Vias                 Yes
    Shapes                        Yes
    Text                          No
    Board                         No
    Drills                        No

Manufacturing

    Drill Breakout                No
    Drill Backoff                 No
    Silkscreen Overlap            No
    Wires                         No
    Component Height              No
    Min Track Width               No
    Neck Length                   No
    Min Annular Ring              No
    Min Paste Size                No

Nets

    Net Completion                No
    Dangling Tracks               Yes

Results

-------



Track to Pad Error (T-P) between (20884.47 23246.97) and (20818.75 23181.25) on Layer "Bottom Copper".
Pad to Pad Error (P-P) between (20687.50 22532.50) and (20712.50 22532.50) on Layer "[Top]".
Track to Via Error (T-V) between (20200.00 20500.00) and (20251.00 20500.00) on Layer "Top Copper".
Track to Track Error (T-T) between (20200.00 21037.50) and (20200.00 21075.00) on Layer "Top Copper".

Number of errors found : 4
End Of Report.