Design Rule Check Report ------------------------ Report File : H:\ProjPCB\ADAC\FPGA\FPGA-AUDIO (PCB - Design Rule Check Report).txt Report Written : Wednesday, September 08, 2010 Design Path : H:\ProjPCB\ADAC\FPGA\FPGA-AUDIO.pcb Design Title : Created : 28.04.2008 12:48:28 Last Saved : 08.09.2010 14:54:52 Editing Time : 1670 min Units : mm (precision 2) Results ------- Pad to Pad error (P-P) at (534.24 574.67) on layer "[All]". Error between Component Pad PL8.7 and Component Pad PL8.6, Gap is 0.00 needs to be 0.25. Pad to Pad error (P-P) at (532.13 575.10) on layer "[All]". Error between Component Pad PL8.7 and Component Pad PL8.10, Gap is 0.00 needs to be 0.25. Pad to Pad error (P-P) at (534.24 582.29) on layer "[All]". Error between Component Pad PL8.8 and Component Pad PL8.9, Gap is 0.00 needs to be 0.25. Pad to Pad error (P-P) at (532.13 580.18) on layer "[All]". Error between Component Pad PL8.8 and Component Pad PL8.11, Gap is 0.00 needs to be 0.25. Gap in Net "DGnd" between (523.24,558.80) and (530.86,556.26) DGnd. Gap in Net "DGnd" between (518.16,543.56) and (524.19,532.13) DGnd. Gap in Net "DGnd" between (524.19,532.13) and (524.19,521.97) DGnd. Gap in Net "DGnd" between (524.19,521.97) and (524.19,516.89) DGnd. Gap in Net "DGnd" between (524.19,516.89) and (524.19,506.73) DGnd. Gap in Net "DGnd" between (524.19,532.13) and (533.40,527.05) DGnd. Gap in Net "DGnd" between (524.19,516.89) and (533.40,511.81) DGnd. Gap in Net "DGnd" between (524.19,521.97) and (513.08,520.70) DGnd. Gap in Net "DGnd" between (513.08,520.70) and (513.08,525.78) DGnd. Gap in Net "DGnd" between (513.08,520.70) and (513.08,515.62) DGnd. Gap in Net "DGnd" between (513.08,515.62) and (513.08,510.54) DGnd. Gap in Net "DGnd" between (513.08,515.62) and (505.46,515.62) DGnd. Gap in Net "DGnd" between (505.46,515.62) and (487.68,510.54) DGnd. Gap in Net "DGnd" between (431.80,584.20) and (435.93,589.15) DGnd. Gap in Net "DGnd" between (431.80,584.20) and (435.93,579.25) DGnd. Gap in Net "DGnd" between (443.75,548.64) and (440.37,557.64) DGnd. Gap in Net "VccoF" between (467.36,533.40) and (440.37,554.24) VccoF. Single pin net FP107 on CONN1.47 at 474.98,543.56 Single pin net FN87 on CONN1.5 at 477.52,518.16 Single pin net FN128 on CONN1.20 at 477.52,556.26 Single pin net FP127 on CONN1.52 at 474.98,556.26 Single pin net FN125 on CONN1.19 at 477.52,553.72 Single pin net FP124 on CONN1.51 at 474.98,553.72 Single pin net FN123 on CONN1.18 at 477.52,551.18 Single pin net FP122 on CONN1.50 at 474.98,551.18 Single pin net FN119 on CONN1.17 at 477.52,548.64 Single pin net FP118 on CONN1.49 at 474.98,548.64 Single pin net FN113 on CONN1.16 at 477.52,546.10 Single pin net FP112 on CONN1.48 at 474.98,546.10 Single pin net FN108 on CONN1.15 at 477.52,543.56 Single pin net N3137 on U6.7 at 518.16,538.48 Gap in Net "Iso" between (531.81,591.82) and (531.81,502.92) Iso. Single pin net PB1 on PL2.2 at 431.80,563.88 Single pin net PB4_SS on PL2.5 at 429.26,558.80 Single pin net PB3 on PL2.4 at 431.80,561.34 Single pin net PB2_Int2 on PL2.3 at 429.26,561.34 Dangling Track from (454.34,546.21) to (454.23,546.10) on layer Bottom Copper Dangling Track from (443.75,508.00) to (443.55,508.00) on layer Bottom Copper Number of errors found : 42 Accepted Errors already in the design ------------------------------------- No errors found Settings -------- Spacings Tracks Yes Pads and Vias Yes Shapes Yes Text No Board No Drills No Components No Manufacturing Drill Breakout No Drill Backoff No Silkscreen Overlap No Wires No Component Height No Copper Text In Board No Min Track Width No Neck Length No Min Annular Ring No Min Paste Size No Vias In Pads No Unplated Vias No Unplated Pads With Inner Tracks No Nets Net Completion Yes Dangling Tracks Yes Net Track Length Differences No End Of Report.