Design Rule Check Report
------------------------

Report File    : H:\ProjPCB\ADAC\FPGA-ISRAM\FPGA (PCB - Design Rule Check Report).txt
Report Written : Monday, August 09, 2010
Project Path   : H:\ProjPCB\ADAC\FPGA-ISRAM\FPGA.prj
Design Path    : H:\ProjPCB\ADAC\FPGA-ISRAM\FPGA.pcb
Design Title   : 
Created        : 14.12.2006 11:34:15
Last Saved     : 09.08.2010 18:07:09
Editing Time   : 31160 min
Units          : thou (precision 2)

Results
-------

Pad to Board Error (P-B) between (1862.50 8100.00) and (1790.00 8100.00) on Layer "[All]".
    Error between Pad (Net 'Iso') and Board, Gap is 68.50 needs to be 175.00.
Track to Pad Error (T-P) between (1953.22 4673.33) and (1975.00 4775.00) on Layer "Top Copper".
    Error between Pad (Net 'Iso') and Track (Net 'N3409!FPGA-RTC!'), Gap is 96.47 needs to be 107.09.
Track to Pad Error (T-P) between (1950.92 4673.79) and (1962.50 4737.50) on Layer "Top Copper".
    Error between Pad (Net 'Iso') and Track (Net 'N3417!FPGA-RTC!'), Gap is 57.25 needs to be 107.09.
Pad to Board Error (P-B) between (1862.50 4600.00) and (1790.00 4600.00) on Layer "[All]".
    Error between Pad (Net 'Iso') and Board, Gap is 68.50 needs to be 175.00.
Pad to Board Error (P-B) between (8086.56 6734.07) and (8105.00 6734.07) on Layer "[All]".
    Error between Component Pad PL16.12 (Net 'DGnd') and Board, Gap is 14.44 needs to be 75.00.
Pad to Board Error (P-B) between (8086.56 7749.07) and (8105.00 7749.07) on Layer "[All]".
    Error between Component Pad PL16.13 (Net 'DGnd') and Board, Gap is 14.44 needs to be 75.00.
Track to Pad Error (T-P) at (4000.00 5197.50) on Layer "Top Copper".
    Error between Component Pad U10.36 and Track (Net 'FP76'), Gap is 0.00 needs to be 7.09.
Track to Text Error (T-X) at (7187.50 4521.00) on Layer "Top Copper".
    Error between Track (Net 'DVcc') and Text, Gap is 0.00 needs to be 10.00.
Track to Text Error (T-X) at (6687.50 4521.00) on Layer "Top Copper".
    Error between Track (Net 'DVcc') and Text, Gap is 0.00 needs to be 10.00.
Via to Text Error (V-X) at (7187.50 4525.00) on Layer "Top Copper".
    Error between Via (Net 'DVcc') and Text, Gap is 0.00 needs to be 10.00.
Component to Component Error (Cm-Cm) at (6841.57 7873.50) on Layer "[Top]".
    R61 - PL16, Gap is 0.00.
Component to Component Error (Cm-Cm) at (5523.05 5942.03) on Layer "[Top]".
    U12 - U11, Gap is 0.00.
Component to Component Error (Cm-Cm) at (4879.00 4950.00) on Layer "[Top]".
    U10 - PL8, Gap is 0.00.
Component to Component Error (Cm-Cm) at (4879.00 7550.00) on Layer "[Top]".
    U9 - PL7, Gap is 0.00.
Component to Component Error (Cm-Cm) at (7714.00 7945.93) on Layer "[Top]".
    LED3 - PL16, Gap is 0.00.
Component to Component Error (Cm-Cm) at (5523.05 6790.00) on Layer "[Top]".
    U11 - C28, Gap is 0.00.
Component to Board Error (Cm-B) at (7650.00 5487.50) on Layer "[Top]".
    CONN1.
Component to Board Error (Cm-B) at (7650.00 5487.50) on Layer "[Top]".
    CONN1.
Component to Component Error (Cm-Cm) at (7273.43 7945.93) on Layer "[Top]".
    PL16 - PL15, Gap is 0.00.
Component to Component Error (Cm-Cm) at (6712.50 5301.50) on Layer "[Top]".
    D3 - C32, Gap is 0.00.
Component to Component Error (Cm-Cm) at (6737.50 4841.50) on Layer "[Bottom]".
    C34 - C36, Gap is 0.00.
Single pin net PC2 on U2.21 at 3306.00,5504.00
Single pin net PD7 on U2.16 at 3149.00,5504.00
Single pin net PD6 on U2.15 at 3117.00,5504.00
Single pin net PD5 on U2.14 at 3086.00,5504.00
Single pin net PD4 on U2.13 at 3054.00,5504.00
Single pin net ARef on U2.29 at 3426.00,5781.00
Gap in Net "Iso" between (1937.50,4600.00) and (1937.50,8100.00) 
    Iso.
Single pin net N2216!FPGA! on U4.7 at 3200.00,5000.00
Single pin net PA7 on U2.30 at 3426.00,5813.00
Single pin net PA6 on U2.31 at 3426.00,5844.00
Single pin net PA5 on U2.32 at 3426.00,5876.00
Single pin net PA4_ADC4 on U2.33 at 3426.00,5907.00
Single pin net PA3_ADC3 on U2.34 at 3337.00,5996.00
Single pin net PA2_ADC2 on U2.35 at 3306.00,5996.00
Single pin net N3137!FPGA-RTC! on U6.7 at 3600.00,7100.00

Number of errors found : 35

Accepted Errors already in the design
-------------------------------------

No errors found

Settings
--------

Spacings

    Tracks                             Yes
    Pads and Vias                      Yes
    Shapes                             Yes
    Text                               Yes
    Board                              Yes
    Drills                             Yes
    Components                         Yes

Manufacturing

    Drill Breakout                     No
    Drill Backoff                      No
    Silkscreen Overlap                 No
    Wires                              No
    Component Height                   No
    Copper Text In Board               No
    Min Track Width                    No
    Neck Length                        No
    Min Annular Ring                   No
    Min Paste Size                     No
    Vias In Pads                       No
    Unplated Vias                      No
    Unplated Pads With Inner Tracks    No

Nets

    Net Completion                     Yes
    Dangling Tracks                    Yes
    Net Track Length Differences       No


End Of Report.