-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : ISE -- / / Filename : port_dec_tb.ant -- /___/ /\ Timestamp : Wed Feb 18 18:55:50 2009 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: port_dec_tb --Device: Xilinx -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY port_dec_tb IS END port_dec_tb; ARCHITECTURE testbench_arch OF port_dec_tb IS FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\ProjFPGA\ct-Atom\main\port_dec_tb.ano"; COMPONENT port_dec PORT ( RAM_ADR : Out std_logic_vector (18 DownTo 0); CPU_ADR : In std_logic_vector (18 DownTo 0); LC_ADR : In std_logic_vector (18 DownTo 0); CPU_DATAo : Out std_logic_vector (7 DownTo 0); CPU_DATAi : In std_logic_vector (7 DownTo 0); CPU_RDn : In std_logic; CPU_WRn : In std_logic; LC_WRn : In std_logic; RAM_OEn : Out std_logic; RAM_WEn : Out std_logic; LC_ENA : In std_logic; LC_DATA : In std_logic_vector (31 DownTo 0); RAM_DATAz : InOut std_logic_vector (7 DownTo 0); PAo : Out std_logic_vector (7 DownTo 0); PBi : In std_logic_vector (7 DownTo 0); PCLo : Out std_logic_vector (3 DownTo 0); PCHi : In std_logic_vector (3 DownTo 0) ); END COMPONENT; SIGNAL RAM_ADR : std_logic_vector (18 DownTo 0) := "0000000000000000000"; SIGNAL CPU_ADR : std_logic_vector (18 DownTo 0) := "0000000000000000000"; SIGNAL LC_ADR : std_logic_vector (18 DownTo 0) := "0000000000000000000"; SIGNAL CPU_DATAo : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL CPU_DATAi : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL CPU_RDn : std_logic := '1'; SIGNAL CPU_WRn : std_logic := '1'; SIGNAL LC_WRn : std_logic := '1'; SIGNAL RAM_OEn : std_logic := '0'; SIGNAL RAM_WEn : std_logic := '0'; SIGNAL LC_ENA : std_logic := '0'; SIGNAL LC_DATA : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000"; SIGNAL RAM_DATAz : std_logic_vector (7 DownTo 0) := "ZZZZZZZZ"; SIGNAL PAo : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL PBi : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL PCLo : std_logic_vector (3 DownTo 0) := "0000"; SIGNAL PCHi : std_logic_vector (3 DownTo 0) := "0000"; SHARED VARIABLE TX_ERROR : INTEGER := 0; SHARED VARIABLE TX_OUT : LINE; BEGIN UUT : port_dec PORT MAP ( RAM_ADR => RAM_ADR, CPU_ADR => CPU_ADR, LC_ADR => LC_ADR, CPU_DATAo => CPU_DATAo, CPU_DATAi => CPU_DATAi, CPU_RDn => CPU_RDn, CPU_WRn => CPU_WRn, LC_WRn => LC_WRn, RAM_OEn => RAM_OEn, RAM_WEn => RAM_WEn, LC_ENA => LC_ENA, LC_DATA => LC_DATA, RAM_DATAz => RAM_DATAz, PAo => PAo, PBi => PBi, PCLo => PCLo, PCHi => PCHi ); PROCESS -- Annotation process VARIABLE TX_TIME : INTEGER := 0; PROCEDURE ANNOTATE_RAM_ADR( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", RAM_ADR, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RAM_ADR); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_CPU_DATAo( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", CPU_DATAo, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CPU_DATAo); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_RAM_OEn( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", RAM_OEn, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RAM_OEn); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_RAM_WEn( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", RAM_WEn, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RAM_WEn); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_PAo( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", PAo, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PAo); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_PCLo( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", PCLo, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCLo); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; BEGIN WAIT for 1 fs; ANNOTATE_RAM_ADR(0); ANNOTATE_CPU_DATAo(0); ANNOTATE_RAM_OEn(0); ANNOTATE_RAM_WEn(0); ANNOTATE_PAo(0); ANNOTATE_PCLo(0); ANNO_LOOP : LOOP WAIT for 10 ns; TX_TIME := TX_TIME + 10; ANNOTATE_RAM_ADR(TX_TIME); ANNOTATE_CPU_DATAo(TX_TIME); ANNOTATE_RAM_OEn(TX_TIME); ANNOTATE_RAM_WEn(TX_TIME); ANNOTATE_PAo(TX_TIME); ANNOTATE_PCLo(TX_TIME); WAIT for 10 ns; TX_TIME := TX_TIME + 10; END LOOP ANNO_LOOP; END PROCESS; PROCESS BEGIN -- ------------- Current Time: 40ns WAIT FOR 40 ns; CPU_ADR <= "0001111111100000000"; CPU_DATAi <= "01010101"; -- ------------------------------------- -- ------------- Current Time: 100ns WAIT FOR 60 ns; RAM_DATAz <= "00100011"; PBi <= "11111111"; -- ------------------------------------- -- ------------- Current Time: 120ns WAIT FOR 20 ns; CPU_RDn <= '0'; -- ------------------------------------- -- ------------- Current Time: 140ns WAIT FOR 20 ns; CPU_RDn <= '1'; -- ------------------------------------- -- ------------- Current Time: 180ns WAIT FOR 40 ns; RAM_DATAz <= "ZZZZZZZZ"; -- ------------------------------------- -- ------------- Current Time: 200ns WAIT FOR 20 ns; CPU_DATAi <= "10101010"; -- ------------------------------------- -- ------------- Current Time: 260ns WAIT FOR 60 ns; CPU_WRn <= '0'; -- ------------------------------------- -- ------------- Current Time: 280ns WAIT FOR 20 ns; CPU_WRn <= '1'; -- ------------------------------------- -- ------------- Current Time: 320ns WAIT FOR 40 ns; PCHi <= "1111"; -- ------------------------------------- -- ------------- Current Time: 360ns WAIT FOR 40 ns; CPU_ADR <= "0001011000000000000"; CPU_DATAi <= "01110111"; -- ------------------------------------- -- ------------- Current Time: 420ns WAIT FOR 60 ns; CPU_WRn <= '0'; -- ------------------------------------- -- ------------- Current Time: 440ns WAIT FOR 20 ns; CPU_WRn <= '1'; -- ------------------------------------- -- ------------- Current Time: 540ns WAIT FOR 100 ns; CPU_DATAi <= "00110011"; -- ------------------------------------- -- ------------- Current Time: 560ns WAIT FOR 20 ns; CPU_ADR <= "0001011000000000001"; -- ------------------------------------- -- ------------- Current Time: 580ns WAIT FOR 20 ns; CPU_RDn <= '0'; -- ------------------------------------- -- ------------- Current Time: 600ns WAIT FOR 20 ns; CPU_RDn <= '1'; -- ------------------------------------- -- ------------- Current Time: 720ns WAIT FOR 120 ns; CPU_DATAi <= "10011001"; -- ------------------------------------- -- ------------- Current Time: 740ns WAIT FOR 20 ns; CPU_ADR <= "0001011000000000010"; -- ------------------------------------- -- ------------- Current Time: 760ns WAIT FOR 20 ns; CPU_WRn <= '0'; -- ------------------------------------- -- ------------- Current Time: 780ns WAIT FOR 20 ns; CPU_WRn <= '1'; -- ------------------------------------- -- ------------- Current Time: 820ns WAIT FOR 40 ns; CPU_RDn <= '0'; -- ------------------------------------- -- ------------- Current Time: 840ns WAIT FOR 20 ns; CPU_RDn <= '1'; -- ------------------------------------- -- ------------- Current Time: 920ns WAIT FOR 80 ns; CPU_ADR <= "0001111111100000000"; -- ------------------------------------- -- ------------- Current Time: 940ns WAIT FOR 20 ns; CPU_RDn <= '0'; RAM_DATAz <= "00010101"; -- ------------------------------------- -- ------------- Current Time: 960ns WAIT FOR 20 ns; CPU_RDn <= '1'; -- ------------------------------------- -- ------------- Current Time: 1000ns WAIT FOR 40 ns; RAM_DATAz <= "ZZZZZZZZ"; -- ------------------------------------- -- ------------- Current Time: 1060ns WAIT FOR 60 ns; CPU_WRn <= '0'; -- ------------------------------------- -- ------------- Current Time: 1080ns WAIT FOR 20 ns; CPU_WRn <= '1'; -- ------------------------------------- WAIT FOR 920 ns; STD.TEXTIO.write(TX_OUT, string'("Total[]")); STD.TEXTIO.writeline(RESULTS, TX_OUT); ASSERT (FALSE) REPORT "Success! Simulation for annotation completed" SEVERITY FAILURE; END PROCESS; END testbench_arch;