-------------------------------------------------------------------------------- -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : sch2vhdl -- / / Filename : main.vhf -- /___/ /\ Timestamp : 11/03/2009 12:44:11 -- \ \ / \ -- \___\/\___\ -- --Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w E:/ProjFPGA/ct-BASIC-LCD/source/main.sch main.vhf --Design Name: main --Device: spartan3 --Purpose: -- This vhdl netlist is translated from an ECS schematic. It can be -- synthesis and simulted, but it should not be modified. -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity main is port ( ClkIn : in std_logic; F_DS : in std_logic; F_MOSI : in std_logic; F_RS : in std_logic; F_SCK : in std_logic; Opto_Rx : in std_logic; PS2_Clk : in std_logic; PS2_Data : in std_logic; Serial_Rx : in std_logic; F_Int : out std_logic; F_MISO : out std_logic; IO600_Rdn : out std_logic; IO600_WRn : out std_logic; LCDCLK : out std_logic; LCDDATA : out std_logic_vector (3 downto 0); LCDFRAME : out std_logic; LCDLOAD : out std_logic; LCDON : out std_logic; OEN : out std_logic; Opto_Tx : out std_logic; Serial_Tx : out std_logic; TestLED : out std_logic; VRAM_A : out std_logic_vector (18 downto 0); WEN : out std_logic; VRAM_D : inout std_logic_vector (7 downto 0)); end main; architecture BEHAVIORAL of main is attribute IOSTANDARD : string ; attribute BOX_TYPE : string ; attribute INIT : string ; signal ComEna : std_logic_vector (7 downto 0); signal ComRx : std_logic_vector (31 downto 0); signal ComTx : std_logic_vector (31 downto 0); signal CPU_Do : std_logic_vector (7 downto 0); signal CPU_RST : std_logic; signal IRQ_ACK : std_logic; signal IRQ_CLR : std_logic; signal IRQ_Source : std_logic_vector (7 downto 0); signal KBD_DWN : std_logic; signal LC_ADR : std_logic_vector (18 downto 0); signal LC_DATA : std_logic_vector (31 downto 0); signal LC_ENA : std_logic; signal LC_OEN : std_logic; signal LC_WEN : std_logic; signal PLOTSYNC : std_logic; signal PS2code : std_logic_vector (31 downto 0); signal P_ADDR : std_logic_vector (15 downto 0); signal P_RD_N : std_logic; signal P_WR_N : std_logic; signal RAMD_RD : std_logic_vector (31 downto 0); signal Rx_data_present : std_logic; signal SPI_Key : std_logic_vector (31 downto 0); signal SPI_KeyStrobe : std_logic; signal Strobe1 : std_logic; signal SYSCLK : std_logic; signal vsync : std_logic; signal XLXN_892 : std_logic_vector (3 downto 0); signal XLXN_917 : std_logic_vector (31 downto 0); signal XLXN_1180 : std_logic_vector (7 downto 0); signal XLXN_1239 : std_logic; signal XLXN_1267 : std_logic; signal XLXN_1490 : std_logic; signal XLXN_1492 : std_logic; signal XLXN_1561 : std_logic; signal XLXN_1585 : std_logic; signal XLXN_1586 : std_logic; signal XLXN_1592 : std_logic; signal XLXN_1639 : std_logic_vector (7 downto 0); signal XLXN_1640 : std_logic; signal XLXN_1641 : std_logic; signal XLXN_1642 : std_logic; signal XLXN_1645 : std_logic; signal XLXN_1648 : std_logic; signal XLXN_1650 : std_logic; signal XLXN_1711 : std_logic; signal XLXN_1712 : std_logic; signal XLXN_1713 : std_logic; signal XLXN_1723 : std_logic; signal XLXN_1724 : std_logic; signal XLXN_1727 : std_logic; signal XLXN_1728 : std_logic_vector (2 downto 0); signal XLXN_1732 : std_logic; signal XLXI_970_INT_0_openSignal : std_logic; signal XLXI_980_D1_openSignal : std_logic_vector (31 downto 0); signal XLXI_984_PIN340_openSignal : std_logic_vector (7 downto 0); signal XLXI_984_PIN341_openSignal : std_logic_vector (7 downto 0); signal XLXI_984_PIN342_openSignal : std_logic_vector (7 downto 0); signal XLXI_984_PIN343_openSignal : std_logic_vector (7 downto 0); component IBUFG port ( I : in std_logic; O : out std_logic); end component; attribute IOSTANDARD of IBUFG : component is "DEFAULT"; attribute BOX_TYPE of IBUFG : component is "BLACK_BOX"; component ps2kbd port ( Rst_n : in std_logic; Clk : in std_logic; PS2_Clk : in std_logic; PS2_Data : in std_logic; Press : out std_logic; Release : out std_logic; Reset : out std_logic; ScanCode : out std_logic_vector (7 downto 0)); end component; component OR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of OR2 : component is "BLACK_BOX"; component INV port ( I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of INV : component is "BLACK_BOX"; component BUF port ( I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of BUF : component is "BLACK_BOX"; component IRQ_latch port ( INT_0 : in std_logic; INT_1 : in std_logic; INT_2 : in std_logic; INT_3 : in std_logic; IRQ_CLR : in std_logic; IRQ_ACK : in std_logic; IRQ_SRC : out std_logic_vector (3 downto 0); IRQ : out std_logic; RST : in std_logic); end component; component SPI_LRC port ( F_DS : in std_logic; F_RS : in std_logic; F_SCLK : in std_logic; F_MOSI : in std_logic; D3 : in std_logic_vector (31 downto 0); D2 : in std_logic_vector (31 downto 0); D1 : in std_logic_vector (31 downto 0); D0 : in std_logic_vector (31 downto 0); SYSCLK : in std_logic; BASEADR : in std_logic_vector (3 downto 0); RAMD_RD : in std_logic_vector (31 downto 0); Q0 : out std_logic_vector (31 downto 0); Q1 : out std_logic_vector (31 downto 0); Q2 : out std_logic_vector (31 downto 0); Q3 : out std_logic_vector (31 downto 0); STROBE0 : out std_logic; STROBE1 : out std_logic; STROBE2 : out std_logic; STROBE3 : out std_logic; LC_OEN : out std_logic; LC_WEN : out std_logic; LC_ADDR : out std_logic_vector (18 downto 0); RAMD_WR : out std_logic_vector (31 downto 0); F_MISO : out std_logic; LC_ENA_0 : out std_logic; LC_ENA_1 : out std_logic; LC_ENA_2 : out std_logic; LC_ENA_3 : out std_logic); end component; component BASIC_glue port ( CLK_X4 : in std_logic; Rx_full : in std_logic; Tx_full : in std_logic; Rx_valid : in std_logic; CPU_RST : in std_logic; CPU_RDn : in std_logic; CPU_WRn : in std_logic; LC_WEn : in std_logic; LC_OEn : in std_logic; LC_ENA : in std_logic; VSYNC : in std_logic; PS2_DWN : in std_logic; PS2_UP : in std_logic; Rx_DATAi : in std_logic_vector (7 downto 0); CPU_ADR : in std_logic_vector (15 downto 0); LC_ADR : in std_logic_vector (18 downto 0); CPU_DATAi : in std_logic_vector (7 downto 0); LC_DATA : in std_logic_vector (31 downto 0); PS2_CODE : in std_logic_vector (7 downto 0); COMin : in std_logic_vector (7 downto 0); IRQsrc : in std_logic_vector (7 downto 0); ASCII : in std_logic_vector (7 downto 0); PIN340 : in std_logic_vector (7 downto 0); PIN341 : in std_logic_vector (7 downto 0); PIN342 : in std_logic_vector (7 downto 0); PIN343 : in std_logic_vector (7 downto 0); RAM_DATAz : inout std_logic_vector (7 downto 0); Tx_write : out std_logic; Rx_ack : out std_logic; Rx_flush : out std_logic; Tx_reset : out std_logic; RAM_OEn : out std_logic; RAM_WEn : out std_logic; VGA_WR : out std_logic; GCMD_WR : out std_logic; TCMD_WR : out std_logic; IRQ_ACK : out std_logic; IRQ_CLR : out std_logic; SER_SEL : out std_logic; DMA : out std_logic; IO600_WEn : out std_logic; IO600_RDn : out std_logic; RAM_ADR : out std_logic_vector (18 downto 0); CPU_DATAo : out std_logic_vector (7 downto 0); Bd_SEL : out std_logic_vector (2 downto 0); COMout : out std_logic_vector (7 downto 0); INTstr : out std_logic_vector (7 downto 0); PORT340 : out std_logic_vector (7 downto 0); PORT341 : out std_logic_vector (7 downto 0); PORT342 : out std_logic_vector (7 downto 0); PORT343 : out std_logic_vector (7 downto 0); PLOTSYNC : in std_logic); end component; component AND3 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3 : component is "BLACK_BOX"; component FD -- synopsys translate_off generic( INIT : bit := '0'); -- synopsys translate_on port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute INIT of FD : component is "0"; attribute BOX_TYPE of FD : component is "BLACK_BOX"; component UART port ( RxD : in std_logic; Tx_Data : in std_logic_vector (7 downto 0); Rx_flush : in std_logic; Tx_write : in std_logic; Rx_ack : in std_logic; Tx_reset : in std_logic; SYSCLK : in std_logic; Rx_Data : out std_logic_vector (7 downto 0); Rx_valid : out std_logic; TxD : out std_logic; Tx_full : out std_logic; Rx_full : out std_logic; BaudSel : in std_logic_vector (2 downto 0)); end component; component GTEXT_LCD320 port ( SYSCLK50 : in std_logic; TXT_WR : in std_logic; DATA : in std_logic_vector (7 downto 0); RESET : in std_logic; ADR : in std_logic_vector (11 downto 0); TCMD_WR : in std_logic; GCMD_WR : in std_logic; GDONE : out std_logic; BLINK : out std_logic; LCDFRAME : out std_logic; LCDLOAD : out std_logic; LCDCLK : out std_logic; LCDON : out std_logic; LCDDATA : out std_logic_vector (3 downto 0); VS_60Hz : out std_logic; PLOTSYNC : out std_logic); end component; component COM_mux port ( UART_Tx : in std_logic; UART_Rx : out std_logic; COM0_Rx : in std_logic; COM1_Tx : out std_logic; COM1_Rx : in std_logic; COM0_Tx : out std_logic; SEL : in std_logic); end component; component t65_wrap port ( RST : in std_logic; IRQ : in std_logic; NMI : in std_logic; HALT : in std_logic; CLK_X4 : in std_logic; DATA_I : in std_logic_vector (7 downto 0); WR_N : out std_logic; HALTED : out std_logic; RD_N : out std_logic; ADDR : out std_logic_vector (15 downto 0); DATA_O : out std_logic_vector (7 downto 0); BUSENA_N : out std_logic); end component; begin XLXN_892(3 downto 0) <= x"4"; XLXN_917(31 downto 0) <= x"24042009"; XLXI_833 : IBUFG port map (I=>ClkIn, O=>SYSCLK); XLXI_884 : ps2kbd port map (Clk=>SYSCLK, PS2_Clk=>PS2_Clk, PS2_Data=>PS2_Data, Rst_n=>XLXN_1492, Press=>KBD_DWN, Release=>XLXN_1239, Reset=>XLXN_1267, ScanCode(7 downto 0)=>PS2code(7 downto 0)); XLXI_894 : OR2 port map (I0=>XLXN_1586, I1=>XLXN_1267, O=>CPU_RST); XLXI_905 : INV port map (I=>XLXN_1732, O=>TestLED); XLXI_963 : BUF port map (I=>ComEna(0), O=>F_Int); XLXI_966 : INV port map (I=>LC_ENA, O=>XLXN_1492); XLXI_970 : IRQ_latch port map (INT_0=>XLXI_970_INT_0_openSignal, INT_1=>Strobe1, INT_2=>Rx_data_present, INT_3=>SPI_KeyStrobe, IRQ_ACK=>IRQ_ACK, IRQ_CLR=>IRQ_CLR, RST=>CPU_RST, IRQ=>XLXN_1490, IRQ_SRC(3 downto 0)=>IRQ_Source(3 downto 0)); XLXI_978_0 : BUF port map (I=>VRAM_D(0), O=>RAMD_RD(24)); XLXI_978_1 : BUF port map (I=>VRAM_D(1), O=>RAMD_RD(25)); XLXI_978_2 : BUF port map (I=>VRAM_D(2), O=>RAMD_RD(26)); XLXI_978_3 : BUF port map (I=>VRAM_D(3), O=>RAMD_RD(27)); XLXI_978_4 : BUF port map (I=>VRAM_D(4), O=>RAMD_RD(28)); XLXI_978_5 : BUF port map (I=>VRAM_D(5), O=>RAMD_RD(29)); XLXI_978_6 : BUF port map (I=>VRAM_D(6), O=>RAMD_RD(30)); XLXI_978_7 : BUF port map (I=>VRAM_D(7), O=>RAMD_RD(31)); XLXI_980 : SPI_LRC port map (BASEADR(3 downto 0)=>XLXN_892(3 downto 0), D0(31 downto 0)=>ComTx(31 downto 0), D1(31 downto 0)=>XLXI_980_D1_openSignal(31 downto 0), D2(31 downto 0)=>PS2code(31 downto 0), D3(31 downto 0)=>XLXN_917(31 downto 0), F_DS=>F_DS, F_MOSI=>F_MOSI, F_RS=>F_RS, F_SCLK=>F_SCK, RAMD_RD(31 downto 0)=>RAMD_RD(31 downto 0), SYSCLK=>SYSCLK, F_MISO=>F_MISO, LC_ADDR(18 downto 0)=>LC_ADR(18 downto 0), LC_ENA_0=>LC_ENA, LC_ENA_1=>open, LC_ENA_2=>open, LC_ENA_3=>open, LC_OEN=>LC_OEN, LC_WEN=>LC_WEN, Q0=>open, Q1(31 downto 0)=>ComRx(31 downto 0), Q2=>open, Q3(31 downto 0)=>SPI_Key(31 downto 0), RAMD_WR(31 downto 0)=>LC_DATA(31 downto 0), STROBE0=>open, STROBE1=>Strobe1, STROBE2=>open, STROBE3=>SPI_KeyStrobe); XLXI_984 : BASIC_glue port map (ASCII(7 downto 0)=>SPI_Key(7 downto 0), CLK_X4=>SYSCLK, COMin(7 downto 0)=>ComRx(7 downto 0), CPU_ADR(15 downto 0)=>P_ADDR(15 downto 0), CPU_DATAi(7 downto 0)=>CPU_Do(7 downto 0), CPU_RDn=>P_RD_N, CPU_RST=>CPU_RST, CPU_WRn=>P_WR_N, IRQsrc(7 downto 0)=>IRQ_Source(7 downto 0), LC_ADR(18 downto 0)=>LC_ADR(18 downto 0), LC_DATA(31 downto 0)=>LC_DATA(31 downto 0), LC_ENA=>XLXN_1561, LC_OEn=>LC_OEN, LC_WEn=>LC_WEN, PIN340(7 downto 0)=>XLXI_984_PIN340_openSignal(7 downto 0), PIN341(7 downto 0)=>XLXI_984_PIN341_openSignal(7 downto 0), PIN342(7 downto 0)=>XLXI_984_PIN342_openSignal(7 downto 0), PIN343(7 downto 0)=>XLXI_984_PIN343_openSignal(7 downto 0), PLOTSYNC=>PLOTSYNC, PS2_CODE(7 downto 0)=>PS2code(7 downto 0), PS2_DWN=>KBD_DWN, PS2_UP=>XLXN_1239, Rx_DATAi(7 downto 0)=>XLXN_1639(7 downto 0), Rx_full=>XLXN_1648, Rx_valid=>Rx_data_present, Tx_full=>XLXN_1645, VSYNC=>vsync, Bd_SEL(2 downto 0)=>XLXN_1728(2 downto 0), COMout(7 downto 0)=>ComTx(31 downto 24), CPU_DATAo(7 downto 0)=>XLXN_1180(7 downto 0), DMA=>XLXN_1732, GCMD_WR=>XLXN_1713, INTstr(7 downto 0)=>ComEna(7 downto 0), IO600_RDn=>IO600_Rdn, IO600_WEn=>IO600_WRn, IRQ_ACK=>IRQ_ACK, IRQ_CLR=>IRQ_CLR, PORT340=>open, PORT341=>open, PORT342=>open, PORT343=>open, RAM_ADR(18 downto 0)=>VRAM_A(18 downto 0), RAM_OEn=>OEN, RAM_WEn=>WEN, Rx_ack=>XLXN_1650, Rx_flush=>XLXN_1641, SER_SEL=>XLXN_1727, TCMD_WR=>XLXN_1712, Tx_reset=>XLXN_1640, Tx_write=>XLXN_1642, VGA_WR=>XLXN_1711, RAM_DATAz(7 downto 0)=>VRAM_D(7 downto 0)); XLXI_990 : AND3 port map (I0=>LC_ENA, I1=>LC_ADR(15), I2=>LC_ADR(14), O=>XLXN_1585); XLXI_994 : FD port map (C=>SYSCLK, D=>XLXN_1585, Q=>XLXN_1586); XLXI_997 : UART port map (BaudSel(2 downto 0)=>XLXN_1728(2 downto 0), RxD=>XLXN_1724, Rx_ack=>XLXN_1650, Rx_flush=>XLXN_1641, SYSCLK=>SYSCLK, Tx_Data(7 downto 0)=>CPU_Do(7 downto 0), Tx_reset=>XLXN_1640, Tx_write=>XLXN_1642, Rx_Data(7 downto 0)=>XLXN_1639(7 downto 0), Rx_full=>XLXN_1648, Rx_valid=>Rx_data_present, TxD=>XLXN_1723, Tx_full=>XLXN_1645); XLXI_1000 : GTEXT_LCD320 port map (ADR(11 downto 0)=>P_ADDR(11 downto 0), DATA(7 downto 0)=>CPU_Do(7 downto 0), GCMD_WR=>XLXN_1713, RESET=>CPU_RST, SYSCLK50=>SYSCLK, TCMD_WR=>XLXN_1712, TXT_WR=>XLXN_1711, BLINK=>open, GDONE=>IRQ_Source(7), LCDCLK=>LCDCLK, LCDDATA(3 downto 0)=>LCDDATA(3 downto 0), LCDFRAME=>LCDFRAME, LCDLOAD=>LCDLOAD, LCDON=>LCDON, PLOTSYNC=>PLOTSYNC, VS_60Hz=>vsync); XLXI_1001 : BUF port map (I=>vsync, O=>XLXN_1592); XLXI_1005 : COM_mux port map (COM0_Rx=>Opto_Rx, COM1_Rx=>Serial_Rx, SEL=>XLXN_1727, UART_Tx=>XLXN_1723, COM0_Tx=>Opto_Tx, COM1_Tx=>Serial_Tx, UART_Rx=>XLXN_1724); XLXI_1011 : t65_wrap port map (CLK_X4=>SYSCLK, DATA_I(7 downto 0)=>XLXN_1180(7 downto 0), HALT=>LC_ENA, IRQ=>XLXN_1490, NMI=>XLXN_1592, RST=>CPU_RST, ADDR(15 downto 0)=>P_ADDR(15 downto 0), BUSENA_N=>open, DATA_O(7 downto 0)=>CPU_Do(7 downto 0), HALTED=>XLXN_1561, RD_N=>P_RD_N, WR_N=>P_WR_N); end BEHAVIORAL;