]> Release 10.1.03 Trace (nt)Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.C:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise E:/ProjFPGA/ct-BASIC-LCD/main/main.ise -intstyle ise -v 3 -s 4 -xml main main.ncd -o main.twr main.pcf -ucf E:/ProjFPGA/ct-BASIC-LCD/source/main.ucf main.ncdmain.pcfxc3s400-4PRODUCTION 1.39 2008-01-09INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.ClkInOpto_Rx1.8410.002PS2_Clk1.0980.598PS2_Data1.2990.436Serial_Rx1.5650.223F_SCKF_MOSI1.3953.009VRAM_D<0>-0.1232.602VRAM_D<1>0.1222.406VRAM_D<2>0.7201.928VRAM_D<3>-0.4902.896VRAM_D<4>0.3782.202VRAM_D<5>0.1422.390VRAM_D<6>-0.2082.671VRAM_D<7>0.2132.333ClkInF_RSF_SCKClkInClkIn17.856F_DS4.3764.376F_RS10.056F_DSF_SCK2.326F_RSF_SCK2.463F_SCKClkIn2.927F_DS4.1024.102F_RS6.965F_SCK3.0274.502F_DSF_MISO17.817Tue Nov 03 12:47:32 2009 TraceTrace Settings Peak Memory Usage: 111 MB