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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : sch2vhdl
--  /   /         Filename : SPI_sro32.vhf
-- /___/   /\     Timestamp : 11/03/2009 12:44:15
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w E:/ProjFPGA/ct-BASIC-LCD/source/SPI_sro32.sch SPI_sro32.vhf
--Design Name: SPI_sro32
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M2_1_MXILINX_SPI_sro32 is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          S0 : in    std_logic; 
          O  : out   std_logic);
end M2_1_MXILINX_SPI_sro32;

architecture BEHAVIORAL of M2_1_MXILINX_SPI_sro32 is
   attribute BOX_TYPE   : string ;
   signal M0 : std_logic;
   signal M1 : std_logic;
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
begin
   I_36_7 : AND2B1
      port map (I0=>S0,
                I1=>D0,
                O=>M0);
   
   I_36_8 : OR2
      port map (I0=>M1,
                I1=>M0,
                O=>O);
   
   I_36_9 : AND2
      port map (I0=>D1,
                I1=>S0,
                O=>M1);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR16CLE_MXILINX_SPI_sro32 is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (15 downto 0); 
          L   : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (15 downto 0));
end SR16CLE_MXILINX_SPI_sro32;

architecture BEHAVIORAL of SR16CLE_MXILINX_SPI_sro32 is
   attribute HU_SET     : string ;
   attribute INIT       : string ;
   attribute BOX_TYPE   : string ;
   signal L_OR_CE : std_logic;
   signal MD0     : std_logic;
   signal MD1     : std_logic;
   signal MD2     : std_logic;
   signal MD3     : std_logic;
   signal MD4     : std_logic;
   signal MD5     : std_logic;
   signal MD6     : std_logic;
   signal MD7     : std_logic;
   signal MD8     : std_logic;
   signal MD9     : std_logic;
   signal MD10    : std_logic;
   signal MD11    : std_logic;
   signal MD12    : std_logic;
   signal MD13    : std_logic;
   signal MD14    : std_logic;
   signal MD15    : std_logic;
   signal Q_DUMMY : std_logic_vector (15 downto 0);
   component M2_1_MXILINX_SPI_sro32
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             S0 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   component FDCE
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute INIT of FDCE : component is "0";
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   attribute HU_SET of I_MQ0 : label is "I_MQ0_0";
   attribute HU_SET of I_MQ1 : label is "I_MQ1_1";
   attribute HU_SET of I_MQ2 : label is "I_MQ2_2";
   attribute HU_SET of I_MQ3 : label is "I_MQ3_3";
   attribute HU_SET of I_MQ4 : label is "I_MQ4_15";
   attribute HU_SET of I_MQ5 : label is "I_MQ5_14";
   attribute HU_SET of I_MQ6 : label is "I_MQ6_13";
   attribute HU_SET of I_MQ7 : label is "I_MQ7_12";
   attribute HU_SET of I_MQ8 : label is "I_MQ8_4";
   attribute HU_SET of I_MQ9 : label is "I_MQ9_5";
   attribute HU_SET of I_MQ10 : label is "I_MQ10_7";
   attribute HU_SET of I_MQ11 : label is "I_MQ11_6";
   attribute HU_SET of I_MQ12 : label is "I_MQ12_11";
   attribute HU_SET of I_MQ13 : label is "I_MQ13_10";
   attribute HU_SET of I_MQ14 : label is "I_MQ14_8";
   attribute HU_SET of I_MQ15 : label is "I_MQ15_9";
begin
   Q(15 downto 0) <= Q_DUMMY(15 downto 0);
   I_MQ0 : M2_1_MXILINX_SPI_sro32
      port map (D0=>SLI,
                D1=>D(0),
                S0=>L,
                O=>MD0);
   
   I_MQ1 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(0),
                D1=>D(1),
                S0=>L,
                O=>MD1);
   
   I_MQ2 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(1),
                D1=>D(2),
                S0=>L,
                O=>MD2);
   
   I_MQ3 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(2),
                D1=>D(3),
                S0=>L,
                O=>MD3);
   
   I_MQ4 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(3),
                D1=>D(4),
                S0=>L,
                O=>MD4);
   
   I_MQ5 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(4),
                D1=>D(5),
                S0=>L,
                O=>MD5);
   
   I_MQ6 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(5),
                D1=>D(6),
                S0=>L,
                O=>MD6);
   
   I_MQ7 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(6),
                D1=>D(7),
                S0=>L,
                O=>MD7);
   
   I_MQ8 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(7),
                D1=>D(8),
                S0=>L,
                O=>MD8);
   
   I_MQ9 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(8),
                D1=>D(9),
                S0=>L,
                O=>MD9);
   
   I_MQ10 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(9),
                D1=>D(10),
                S0=>L,
                O=>MD10);
   
   I_MQ11 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(10),
                D1=>D(11),
                S0=>L,
                O=>MD11);
   
   I_MQ12 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(11),
                D1=>D(12),
                S0=>L,
                O=>MD12);
   
   I_MQ13 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(12),
                D1=>D(13),
                S0=>L,
                O=>MD13);
   
   I_MQ14 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(13),
                D1=>D(14),
                S0=>L,
                O=>MD14);
   
   I_MQ15 : M2_1_MXILINX_SPI_sro32
      port map (D0=>Q_DUMMY(14),
                D1=>D(15),
                S0=>L,
                O=>MD15);
   
   I_Q0 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD0,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD1,
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD2,
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD3,
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD4,
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD5,
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD6,
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD7,
                Q=>Q_DUMMY(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD8,
                Q=>Q_DUMMY(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD9,
                Q=>Q_DUMMY(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD10,
                Q=>Q_DUMMY(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD11,
                Q=>Q_DUMMY(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD12,
                Q=>Q_DUMMY(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD13,
                Q=>Q_DUMMY(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD14,
                Q=>Q_DUMMY(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD15,
                Q=>Q_DUMMY(15));
   
   I_36_67 : OR2
      port map (I0=>L,
                I1=>CE,
                O=>L_OR_CE);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI_sro32 is
   port ( D     : in    std_logic_vector (31 downto 0); 
          N_SEL : in    std_logic; 
          SCLK  : in    std_logic; 
          MISO  : out   std_logic);
end SPI_sro32;

architecture BEHAVIORAL of SPI_sro32 is
   attribute BOX_TYPE   : string ;
   attribute INIT       : string ;
   attribute HU_SET     : string ;
   signal Q0H                     : std_logic_vector (15 downto 0);
   signal Q0L                     : std_logic_vector (15 downto 0);
   signal SPI_CLKINV              : std_logic;
   signal SSDATN                  : std_logic;
   signal XLXN_284                : std_logic;
   signal XLXN_357                : std_logic;
   signal XLXN_365                : std_logic;
   signal XLXI_219_SLI_openSignal : std_logic;
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component FDC
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute INIT of FDC : component is "0";
   attribute BOX_TYPE of FDC : component is "BLACK_BOX";
   
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component SR16CLE_MXILINX_SPI_sro32
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (15 downto 0); 
             L   : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   attribute HU_SET of XLXI_218 : label is "XLXI_218_16";
   attribute HU_SET of XLXI_219 : label is "XLXI_219_17";
begin
   XLXI_4 : GND
      port map (G=>XLXN_365);
   
   XLXI_119 : INV
      port map (I=>N_SEL,
                O=>SSDATN);
   
   XLXI_199 : FDC
      port map (C=>SPI_CLKINV,
                CLR=>N_SEL,
                D=>SSDATN,
                Q=>XLXN_284);
   
   XLXI_200 : INV
      port map (I=>XLXN_284,
                O=>XLXN_357);
   
   XLXI_214 : INV
      port map (I=>SCLK,
                O=>SPI_CLKINV);
   
   XLXI_217 : AND2B1
      port map (I0=>N_SEL,
                I1=>Q0H(15),
                O=>MISO);
   
   XLXI_218 : SR16CLE_MXILINX_SPI_sro32
      port map (C=>SPI_CLKINV,
                CE=>SSDATN,
                CLR=>XLXN_365,
                D(15 downto 0)=>D(31 downto 16),
                L=>XLXN_357,
                SLI=>Q0L(15),
                Q(15 downto 0)=>Q0H(15 downto 0));
   
   XLXI_219 : SR16CLE_MXILINX_SPI_sro32
      port map (C=>SPI_CLKINV,
                CE=>SSDATN,
                CLR=>XLXN_365,
                D(15 downto 0)=>D(15 downto 0),
                L=>XLXN_357,
                SLI=>XLXI_219_SLI_openSignal,
                Q(15 downto 0)=>Q0L(15 downto 0));
   
end BEHAVIORAL;