-------------------------------------------------------------------------------- -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : sch2vhdl -- / / Filename : SPI_LRC.vhf -- /___/ /\ Timestamp : 11/03/2009 12:44:12 -- \ \ / \ -- \___\/\___\ -- --Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w E:/ProjFPGA/ct-BASIC-LCD/source/SPI_LRC.sch SPI_LRC.vhf --Design Name: SPI_LRC --Device: spartan3 --Purpose: -- This vhdl netlist is translated from an ECS schematic. It can be -- synthesis and simulted, but it should not be modified. -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity D2_4E_MXILINX_SPI_LRC is port ( A0 : in std_logic; A1 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic); end D2_4E_MXILINX_SPI_LRC; architecture BEHAVIORAL of D2_4E_MXILINX_SPI_LRC is attribute BOX_TYPE : string ; component AND3 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3 : component is "BLACK_BOX"; component AND3B1 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX"; component AND3B2 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX"; begin I_36_30 : AND3 port map (I0=>A1, I1=>A0, I2=>E, O=>D3); I_36_31 : AND3B1 port map (I0=>A0, I1=>A1, I2=>E, O=>D2); I_36_32 : AND3B1 port map (I0=>A1, I1=>A0, I2=>E, O=>D1); I_36_33 : AND3B2 port map (I0=>A0, I1=>A1, I2=>E, O=>D0); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity FD8CE_MXILINX_SPI_LRC is port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic_vector (7 downto 0); Q : out std_logic_vector (7 downto 0)); end FD8CE_MXILINX_SPI_LRC; architecture BEHAVIORAL of FD8CE_MXILINX_SPI_LRC is attribute INIT : string ; attribute BOX_TYPE : string ; component FDCE -- synopsys translate_off generic( INIT : bit := '0'); -- synopsys translate_on port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute INIT of FDCE : component is "0"; attribute BOX_TYPE of FDCE : component is "BLACK_BOX"; begin I_Q0 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(0), Q=>Q(0)); I_Q1 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(1), Q=>Q(1)); I_Q2 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(2), Q=>Q(2)); I_Q3 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(3), Q=>Q(3)); I_Q4 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(4), Q=>Q(4)); I_Q5 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(5), Q=>Q(5)); I_Q6 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(6), Q=>Q(6)); I_Q7 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D(7), Q=>Q(7)); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity COMP4_MXILINX_SPI_LRC is port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; B0 : in std_logic; B1 : in std_logic; B2 : in std_logic; B3 : in std_logic; EQ : out std_logic); end COMP4_MXILINX_SPI_LRC; architecture BEHAVIORAL of COMP4_MXILINX_SPI_LRC is attribute BOX_TYPE : string ; signal AB0 : std_logic; signal AB1 : std_logic; signal AB2 : std_logic; signal AB3 : std_logic; component AND4 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4 : component is "BLACK_BOX"; component XNOR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of XNOR2 : component is "BLACK_BOX"; begin I_36_32 : AND4 port map (I0=>AB3, I1=>AB2, I2=>AB1, I3=>AB0, O=>EQ); I_36_33 : XNOR2 port map (I0=>B2, I1=>A2, O=>AB2); I_36_34 : XNOR2 port map (I0=>B3, I1=>A3, O=>AB3); I_36_42 : XNOR2 port map (I0=>B1, I1=>A1, O=>AB1); I_36_43 : XNOR2 port map (I0=>B0, I1=>A0, O=>AB0); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity D3_8E_MXILINX_SPI_LRC is port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic; D4 : out std_logic; D5 : out std_logic; D6 : out std_logic; D7 : out std_logic); end D3_8E_MXILINX_SPI_LRC; architecture BEHAVIORAL of D3_8E_MXILINX_SPI_LRC is attribute BOX_TYPE : string ; component AND4 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4 : component is "BLACK_BOX"; component AND4B1 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX"; component AND4B2 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX"; component AND4B3 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX"; begin I_36_30 : AND4 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D7); I_36_31 : AND4B1 port map (I0=>A0, I1=>A2, I2=>A1, I3=>E, O=>D6); I_36_32 : AND4B1 port map (I0=>A1, I1=>A2, I2=>A0, I3=>E, O=>D5); I_36_33 : AND4B2 port map (I0=>A1, I1=>A0, I2=>A2, I3=>E, O=>D4); I_36_34 : AND4B1 port map (I0=>A2, I1=>A0, I2=>A1, I3=>E, O=>D3); I_36_35 : AND4B2 port map (I0=>A2, I1=>A0, I2=>A1, I3=>E, O=>D2); I_36_36 : AND4B2 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D1); I_36_37 : AND4B3 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D0); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity SPI_LRC is port ( BASEADR : in std_logic_vector (3 downto 0); D0 : in std_logic_vector (31 downto 0); D1 : in std_logic_vector (31 downto 0); D2 : in std_logic_vector (31 downto 0); D3 : in std_logic_vector (31 downto 0); F_DS : in std_logic; F_MOSI : in std_logic; F_RS : in std_logic; F_SCLK : in std_logic; RAMD_RD : in std_logic_vector (31 downto 0); SYSCLK : in std_logic; F_MISO : out std_logic; LC_ADDR : out std_logic_vector (18 downto 0); LC_ENA_0 : out std_logic; LC_ENA_1 : out std_logic; LC_ENA_2 : out std_logic; LC_ENA_3 : out std_logic; LC_OEN : out std_logic; LC_WEN : out std_logic; Q0 : out std_logic_vector (31 downto 0); Q1 : out std_logic_vector (31 downto 0); Q2 : out std_logic_vector (31 downto 0); Q3 : out std_logic_vector (31 downto 0); RAMD_WR : out std_logic_vector (31 downto 0); STROBE0 : out std_logic; STROBE1 : out std_logic; STROBE2 : out std_logic; STROBE3 : out std_logic); end SPI_LRC; architecture BEHAVIORAL of SPI_LRC is attribute HU_SET : string ; attribute BOX_TYPE : string ; attribute INIT : string ; attribute IOSTANDARD : string ; attribute SLEW : string ; attribute DRIVE : string ; signal BASE_LC : std_logic_vector (3 downto 0); signal BASE_RNG : std_logic; signal CORESEL : std_logic_vector (7 downto 0); signal F_MISO_Z : std_logic; signal LC_RNG : std_logic; signal LC128 : std_logic; signal LC129 : std_logic; signal LC130 : std_logic; signal LC131 : std_logic; signal PRESTRB0 : std_logic; signal PRESTRB1 : std_logic; signal PRESTRB2 : std_logic; signal PRESTRB3 : std_logic; signal RAMINCR_128 : std_logic; signal REGSEL : std_logic_vector (7 downto 0); signal SRD : std_logic_vector (31 downto 0); signal START : std_logic_vector (31 downto 0); signal STR_129 : std_logic; signal STR_130 : std_logic; signal STR_131 : std_logic; signal XLXN_1081 : std_logic; signal XLXN_1102 : std_logic; signal XLXN_1103 : std_logic; signal XLXN_1104 : std_logic; signal XLXN_1105 : std_logic; signal XLXN_1133 : std_logic_vector (31 downto 0); signal XLXN_1155 : std_logic; signal XLXN_1160 : std_logic; signal XLXN_1166 : std_logic; signal XLXN_1168 : std_logic; signal XLXN_1171 : std_logic; signal XLXN_1535 : std_logic; signal XLXN_1541 : std_logic; signal XLXN_1550 : std_logic; signal XLXN_1551 : std_logic; signal XLXN_1557 : std_logic; signal XLXN_1571 : std_logic; signal XLXN_1595 : std_logic; signal XLXN_1605 : std_logic; signal XLXI_538_CLR_openSignal : std_logic; component COMP4_MXILINX_SPI_LRC port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; B0 : in std_logic; B1 : in std_logic; B2 : in std_logic; B3 : in std_logic; EQ : out std_logic); end component; component SPI_sri8 port ( N_SEL : in std_logic; MOSI : in std_logic; SCLK : in std_logic; SYSCLK : in std_logic; Q : out std_logic_vector (7 downto 0); STROBE : out std_logic); end component; component SPI_sri32 port ( DQ : out std_logic_vector (31 downto 0); STROBE : out std_logic; SYSCLK : in std_logic; SCLK : in std_logic; N_SEL : in std_logic; MOSI : in std_logic); end component; component SPI_sro32 port ( MISO : out std_logic; D : in std_logic_vector (31 downto 0); SCLK : in std_logic; N_SEL : in std_logic); end component; component SPI_reg32 port ( Q : out std_logic_vector (31 downto 0); STROBE : out std_logic; D : in std_logic_vector (31 downto 0); ENA : in std_logic; SYSCLK : in std_logic); end component; component AND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND2 : component is "BLACK_BOX"; component SPI_inmux4 port ( CLK : in std_logic; SEL : in std_logic_vector (1 downto 0); D0 : in std_logic_vector (31 downto 0); D1 : in std_logic_vector (31 downto 0); D2 : in std_logic_vector (31 downto 0); D3 : in std_logic_vector (31 downto 0); Q : out std_logic_vector (31 downto 0); ENA : in std_logic); end component; component D2_4E_MXILINX_SPI_LRC port ( A0 : in std_logic; A1 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic); end component; component AND2B2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND2B2 : component is "BLACK_BOX"; component AND3 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3 : component is "BLACK_BOX"; component FD -- synopsys translate_off generic( INIT : bit := '0'); -- synopsys translate_on port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute INIT of FD : component is "0"; attribute BOX_TYPE of FD : component is "BLACK_BOX"; component COUNT_LRC port ( SYSCLK : in std_logic; LOADSTR : in std_logic; READSTR : in std_logic; RAMINCR : in std_logic; ENARST : in std_logic; START : in std_logic_vector (18 downto 0); LC_ENA : out std_logic; LC_WEN : out std_logic; LC_OEN : out std_logic; LC_ADDR : out std_logic_vector (18 downto 0)); end component; component D3_8E_MXILINX_SPI_LRC port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic; D4 : out std_logic; D5 : out std_logic; D6 : out std_logic; D7 : out std_logic); end component; component FD8CE_MXILINX_SPI_LRC port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic_vector (7 downto 0); Q : out std_logic_vector (7 downto 0)); end component; component OR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of OR2 : component is "BLACK_BOX"; component OBUFT port ( I : in std_logic; T : in std_logic; O : out std_logic); end component; attribute IOSTANDARD of OBUFT : component is "DEFAULT"; attribute SLEW of OBUFT : component is "SLOW"; attribute DRIVE of OBUFT : component is "12"; attribute BOX_TYPE of OBUFT : component is "BLACK_BOX"; component NAND2B1 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of NAND2B1 : component is "BLACK_BOX"; attribute HU_SET of XLXI_419 : label is "XLXI_419_1"; attribute HU_SET of XLXI_499 : label is "XLXI_499_0"; attribute HU_SET of XLXI_500 : label is "XLXI_500_2"; attribute HU_SET of XLXI_525 : label is "XLXI_525_3"; attribute HU_SET of XLXI_536 : label is "XLXI_536_4"; attribute HU_SET of XLXI_538 : label is "XLXI_538_5"; attribute HU_SET of XLXI_608 : label is "XLXI_608_6"; begin BASE_LC(3 downto 0) <= x"8"; XLXI_419 : COMP4_MXILINX_SPI_LRC port map (A0=>REGSEL(4), A1=>REGSEL(5), A2=>REGSEL(6), A3=>REGSEL(7), B0=>BASEADR(0), B1=>BASEADR(1), B2=>BASEADR(2), B3=>BASEADR(3), EQ=>BASE_RNG); XLXI_480 : SPI_sri8 port map (MOSI=>F_MOSI, N_SEL=>F_RS, SCLK=>F_SCLK, SYSCLK=>SYSCLK, Q(7 downto 0)=>REGSEL(7 downto 0), STROBE=>XLXN_1171); XLXI_481 : SPI_sri32 port map (MOSI=>F_MOSI, N_SEL=>F_DS, SCLK=>F_SCLK, SYSCLK=>SYSCLK, DQ(31 downto 0)=>SRD(31 downto 0), STROBE=>XLXN_1081); XLXI_482 : SPI_sro32 port map (D(31 downto 0)=>XLXN_1133(31 downto 0), N_SEL=>XLXN_1551, SCLK=>F_SCLK, MISO=>XLXN_1571); XLXI_487 : SPI_reg32 port map (D(31 downto 0)=>SRD(31 downto 0), ENA=>XLXN_1105, SYSCLK=>SYSCLK, Q(31 downto 0)=>Q3(31 downto 0), STROBE=>STROBE3); XLXI_488 : SPI_reg32 port map (D(31 downto 0)=>SRD(31 downto 0), ENA=>XLXN_1104, SYSCLK=>SYSCLK, Q(31 downto 0)=>Q2(31 downto 0), STROBE=>STROBE2); XLXI_490 : AND2 port map (I0=>LC_RNG, I1=>XLXN_1081, O=>XLXN_1155); XLXI_494 : SPI_reg32 port map (D(31 downto 0)=>SRD(31 downto 0), ENA=>XLXN_1103, SYSCLK=>SYSCLK, Q(31 downto 0)=>Q1(31 downto 0), STROBE=>STROBE1); XLXI_495 : SPI_reg32 port map (D(31 downto 0)=>SRD(31 downto 0), ENA=>XLXN_1102, SYSCLK=>SYSCLK, Q(31 downto 0)=>Q0(31 downto 0), STROBE=>STROBE0); XLXI_498 : SPI_inmux4 port map (CLK=>SYSCLK, D0(31 downto 0)=>D0(31 downto 0), D1(31 downto 0)=>D1(31 downto 0), D2(31 downto 0)=>D2(31 downto 0), D3(31 downto 0)=>D3(31 downto 0), ENA=>BASE_RNG, SEL(1 downto 0)=>REGSEL(1 downto 0), Q(31 downto 0)=>XLXN_1133(31 downto 0)); XLXI_499 : D2_4E_MXILINX_SPI_LRC port map (A0=>REGSEL(0), A1=>REGSEL(1), E=>XLXN_1160, D0=>XLXN_1102, D1=>XLXN_1103, D2=>XLXN_1104, D3=>XLXN_1105); XLXI_500 : D2_4E_MXILINX_SPI_LRC port map (A0=>REGSEL(0), A1=>REGSEL(1), E=>XLXN_1166, D0=>PRESTRB0, D1=>PRESTRB1, D2=>PRESTRB2, D3=>PRESTRB3); XLXI_501 : AND2B2 port map (I0=>REGSEL(3), I1=>REGSEL(2), O=>XLXN_1168); XLXI_503 : AND3 port map (I0=>BASE_RNG, I1=>XLXN_1168, I2=>XLXN_1081, O=>XLXN_1160); XLXI_505 : AND3 port map (I0=>XLXN_1171, I1=>XLXN_1168, I2=>BASE_RNG, O=>XLXN_1166); XLXI_506 : FD port map (C=>SYSCLK, D=>LC131, Q=>STR_131); XLXI_507 : COUNT_LRC port map (ENARST=>STR_129, LOADSTR=>STR_130, RAMINCR=>RAMINCR_128, READSTR=>STR_131, START(18 downto 0)=>START(18 downto 0), SYSCLK=>SYSCLK, LC_ADDR(18 downto 0)=>LC_ADDR(18 downto 0), LC_ENA=>XLXN_1605, LC_OEN=>LC_OEN, LC_WEN=>LC_WEN); XLXI_508 : SPI_reg32 port map (D(31 downto 0)=>SRD(31 downto 0), ENA=>XLXN_1595, SYSCLK=>SYSCLK, Q(31 downto 0)=>START(31 downto 0), STROBE=>open); XLXI_525 : D3_8E_MXILINX_SPI_LRC port map (A0=>REGSEL(0), A1=>REGSEL(1), A2=>REGSEL(2), E=>XLXN_1155, D0=>LC128, D1=>LC129, D2=>LC130, D3=>LC131, D4=>open, D5=>open, D6=>open, D7=>open); XLXI_527 : SPI_sro32 port map (D(31 downto 0)=>RAMD_RD(31 downto 0), N_SEL=>XLXN_1550, SCLK=>F_SCLK, MISO=>XLXN_1535); XLXI_536 : COMP4_MXILINX_SPI_LRC port map (A0=>REGSEL(4), A1=>REGSEL(5), A2=>REGSEL(6), A3=>REGSEL(7), B0=>BASE_LC(0), B1=>BASE_LC(1), B2=>BASE_LC(2), B3=>BASE_LC(3), EQ=>LC_RNG); XLXI_538 : FD8CE_MXILINX_SPI_LRC port map (C=>SYSCLK, CE=>LC129, CLR=>XLXI_538_CLR_openSignal, D(7 downto 0)=>SRD(7 downto 0), Q(7 downto 0)=>CORESEL(7 downto 0)); XLXI_539 : SPI_reg32 port map (D(31 downto 0)=>SRD(31 downto 0), ENA=>LC128, SYSCLK=>SYSCLK, Q(31 downto 0)=>RAMD_WR(31 downto 0), STROBE=>RAMINCR_128); XLXI_587 : OR2 port map (I0=>XLXN_1571, I1=>XLXN_1535, O=>XLXN_1541); XLXI_589 : OBUFT port map (I=>XLXN_1541, T=>F_MISO_Z, O=>F_MISO); XLXI_594 : NAND2B1 port map (I0=>F_DS, I1=>XLXN_1557, O=>F_MISO_Z); XLXI_598 : OR2 port map (I0=>LC_RNG, I1=>BASE_RNG, O=>XLXN_1557); XLXI_603 : NAND2B1 port map (I0=>F_DS, I1=>LC_RNG, O=>XLXN_1550); XLXI_604 : NAND2B1 port map (I0=>F_DS, I1=>BASE_RNG, O=>XLXN_1551); XLXI_605 : FD port map (C=>SYSCLK, D=>LC129, Q=>STR_129); XLXI_606 : OR2 port map (I0=>LC131, I1=>LC130, O=>XLXN_1595); XLXI_607 : FD port map (C=>SYSCLK, D=>LC130, Q=>STR_130); XLXI_608 : D2_4E_MXILINX_SPI_LRC port map (A0=>CORESEL(0), A1=>CORESEL(1), E=>XLXN_1605, D0=>LC_ENA_0, D1=>LC_ENA_1, D2=>LC_ENA_2, D3=>LC_ENA_3); end BEHAVIORAL;