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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : sch2vhdl
--  /   /         Filename : IRQ_latch.vhf
-- /___/   /\     Timestamp : 11/03/2009 12:44:18
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w E:/ProjFPGA/ct-BASIC-LCD/source/IRQ_latch.sch IRQ_latch.vhf
--Design Name: IRQ_latch
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity IRQ_latch is
   port ( INT_0   : in    std_logic; 
          INT_1   : in    std_logic; 
          INT_2   : in    std_logic; 
          INT_3   : in    std_logic; 
          IRQ_ACK : in    std_logic; 
          IRQ_CLR : in    std_logic; 
          RST     : in    std_logic; 
          IRQ     : out   std_logic; 
          IRQ_SRC : out   std_logic_vector (3 downto 0));
end IRQ_latch;

architecture BEHAVIORAL of IRQ_latch is
   attribute INIT       : string ;
   attribute BOX_TYPE   : string ;
   signal IRQ_ACK_int         : std_logic;
   signal IRQ_CLR_int         : std_logic;
   signal XLXN_5              : std_logic;
   signal XLXI_3_C_openSignal : std_logic;
   signal XLXI_3_D_openSignal : std_logic;
   signal XLXI_5_C_openSignal : std_logic;
   signal XLXI_5_D_openSignal : std_logic;
   signal XLXI_6_C_openSignal : std_logic;
   signal XLXI_6_D_openSignal : std_logic;
   signal XLXI_7_C_openSignal : std_logic;
   signal XLXI_7_D_openSignal : std_logic;
   signal XLXI_8_C_openSignal : std_logic;
   signal XLXI_8_D_openSignal : std_logic;
   component FDCP
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             PRE : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute INIT of FDCP : component is "0";
   attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
   
   component OR4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
begin
   XLXI_3 : FDCP
      port map (C=>XLXI_3_C_openSignal,
                CLR=>IRQ_CLR_int,
                D=>XLXI_3_D_openSignal,
                PRE=>INT_0,
                Q=>IRQ_SRC(0));
   
   XLXI_5 : FDCP
      port map (C=>XLXI_5_C_openSignal,
                CLR=>IRQ_CLR_int,
                D=>XLXI_5_D_openSignal,
                PRE=>INT_1,
                Q=>IRQ_SRC(1));
   
   XLXI_6 : FDCP
      port map (C=>XLXI_6_C_openSignal,
                CLR=>IRQ_CLR_int,
                D=>XLXI_6_D_openSignal,
                PRE=>INT_2,
                Q=>IRQ_SRC(2));
   
   XLXI_7 : FDCP
      port map (C=>XLXI_7_C_openSignal,
                CLR=>IRQ_CLR_int,
                D=>XLXI_7_D_openSignal,
                PRE=>INT_3,
                Q=>IRQ_SRC(3));
   
   XLXI_8 : FDCP
      port map (C=>XLXI_8_C_openSignal,
                CLR=>IRQ_ACK_int,
                D=>XLXI_8_D_openSignal,
                PRE=>XLXN_5,
                Q=>IRQ);
   
   XLXI_9 : OR4
      port map (I0=>INT_0,
                I1=>INT_1,
                I2=>INT_2,
                I3=>INT_3,
                O=>XLXN_5);
   
   XLXI_10 : OR2
      port map (I0=>RST,
                I1=>IRQ_CLR,
                O=>IRQ_CLR_int);
   
   XLXI_11 : OR2
      port map (I0=>RST,
                I1=>IRQ_ACK,
                O=>IRQ_ACK_int);
   
end BEHAVIORAL;