Xilinx Design Summary

main Project Status (11/03/2009 - 08:00:47)
Project File:	main.ise	Current State:	Programming File Generated
Module Name:	main	Errors:	No Errors
Target Device:	xc3s400-4tq144	Warnings:	474 Warnings
Product Version:	ISE 10.1.03 - WebPACK	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

main Partition Summary				[-]
No partition information was found.

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	1,007	7,168	14%
Number used as Flip Flops	862
Number used as Latches	145
Number of 4 input LUTs	2,271	7,168	31%
Logic Distribution
Number of occupied Slices	1,477	3,584	41%
Number of Slices containing only related logic	1,477	1,477	100%
Number of Slices containing unrelated logic	0	1,477	0%
Total Number of 4 input LUTs	2,406	7,168	33%
Number used as logic	2,235
Number used as a route-thru	135
Number used as Shift registers	36
Number of bonded IOBs
Number of bonded	53	97	54%
IOB Latches	5
Number of RAMB16s	9	16	56%
Number of MULT18X18s	1	16	6%
Number of BUFGMUXs	8	8	100%
Number of RPM macros	8

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

Date Generated: 11/03/2009 - 08:00:48