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-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 14.7
--  \   \         Application : sch2hdl
--  /   /         Filename : main_fbas.vhf
-- /___/   /\     Timestamp : 04/28/2016 14:42:53
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl E:/Dropbox/CTLAB_FBAS/main_fbas.vhf -w E:/Dropbox/CTLAB_FBAS/main_fbas.sch
--Design Name: main_fbas
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity main_fbas is
   port ( F_DS   : in    std_logic; 
          F_MOSI : in    std_logic; 
          F_RS   : in    std_logic; 
          F_SCK  : in    std_logic; 
          SYSCLK : in    std_logic; 
          F_MISO : out   std_logic; 
          SYNC   : out   std_logic; 
          VIDEO  : out   std_logic_vector (2 downto 0));
end main_fbas;

architecture BEHAVIORAL of main_fbas is
   signal XLXN_306 : std_logic_vector (31 downto 0);
   component fbas_count
      port ( SYSCLK : in    std_logic; 
             SYNC   : out   std_logic; 
             VIDEO  : out   std_logic_vector (2 downto 0));
   end component;
   
begin
   XLXN_306(31 downto 0) <= x"04122008";
   XLXI_345 : fbas_count
      port map (SYSCLK=>SYSCLK,
                SYNC=>SYNC,
                VIDEO(2 downto 0)=>VIDEO(2 downto 0));
   
end BEHAVIORAL;