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Release 14.7 Trace  (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml main_fbas.twx main_fbas.ncd -o main_fbas.twr main_fbas.pcf

Design file:              main_fbas.ncd
Physical constraint file: main_fbas.pcf
Device,package,speed:     xc3s400,tq144,-4 (PRODUCTION 1.39 2013-10-13)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock F_SCK
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
F_MOSI      |   -0.646(R)|    3.271(R)|F_SCK_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock F_DS to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
LED         |   13.443(R)|F_DS_IBUF         |   0.000|
------------+------------+------------------+--------+

Clock F_RS to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
F_MISO      |   16.255(R)|F_RS_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock F_SCK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
F_MISO      |   14.141(F)|F_SCK_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock SYSCLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
SYNC        |   13.101(R)|SYSCLK_BUFGP      |   0.000|
VIDEO<0>    |   12.268(R)|SYSCLK_BUFGP      |   0.000|
VIDEO<2>    |   18.208(R)|SYSCLK_BUFGP      |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock F_DS
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
F_RS           |    4.184|         |         |         |
F_SCK          |    1.658|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock F_RS
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
F_SCK          |    1.678|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock F_SCK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
F_DS           |         |         |    3.115|    3.115|
F_SCK          |    2.008|         |         |    3.557|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock SYSCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SYSCLK         |    5.386|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
F_DS           |F_MISO         |   12.286|
---------------+---------------+---------+


Analysis completed Thu Apr 28 16:17:48 2016 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 164 MB