fbas_count Project Status (04/28/2016 - 12:49:14)
Project File: main.xise Parser Errors: No Errors
Module Name: fbas_count Implementation State: Synthesized (Failed)
Target Device: xc3s400-4tq144
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 40 3584 1%
Number of Slice Flip Flops 45 7168 0%
Number of 4 input LUTs 79 7168 1%
Number of bonded IOBs 5 97 5%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo 28. Apr 12:49:01 201601 Warning (0 new)0
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 04/28/2016 - 14:35:58