Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s400
Project ID (random number) 4e1efdf5e9aa4373aadfd4b1929c877c.5A4CD53EDB914E4F8C287B80FCD973BF.9 Target Package: tq144
Registration ID 174235926_0_0_175 Target Speed: -4
Date Generated 2016-04-28T16:17:56 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name AMD Phenom(tm) 8750 Triple-Core Processor CPU Speed 2400 MHz
CPU Name AMD Phenom(tm) 8750 Triple-Core Processor CPU Speed 2400 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=2
  • 10-bit up accumulator=2
 Adders/Subtractors=4
  • 10-bit adder=4
 Comparators=7
  • 10-bit comparator lessequal=1
  • 11-bit comparator greatequal=4
  • 11-bit comparator lessequal=2
 Counters=3
  • 10-bit up counter=2
  • 6-bit up counter=1
 Registers=347
  • Flip-Flops=347
 Xors=3
  • 1-bit xor2=2
  • 1-bit xor4=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=11
  • AGG_IO=11
  • AGG_SLICE=125
  • NUM_4_INPUT_LUT=219
  • NUM_BONDED_IOB=11
  • NUM_BUFGMUX=5
  • NUM_CYMUX=76
  • NUM_LUT_RT=18
  • NUM_SHIFT=2
  • NUM_SLICEL=124
  • NUM_SLICEM=1
  • NUM_SLICE_FF=124
  • NUM_XOR=40
 		NetStatistics
  • NumNets_Active=253
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=69
  • NumNodesOfType_Active_CNTRLPIN=59
  • NumNodesOfType_Active_DOUBLE=481
  • NumNodesOfType_Active_DUMMY=573
  • NumNodesOfType_Active_DUMMYESC=5
  • NumNodesOfType_Active_GLOBAL=42
  • NumNodesOfType_Active_HFULLHEX=3
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_HUNIHEX=15
  • NumNodesOfType_Active_INPUT=640
  • NumNodesOfType_Active_IOBOUTPUT=5
  • NumNodesOfType_Active_OMUX=274
  • NumNodesOfType_Active_OUTPUT=241
  • NumNodesOfType_Active_PREBXBY=34
  • NumNodesOfType_Active_VFULLHEX=11
  • NumNodesOfType_Active_VUNIHEX=11
  • NumNodesOfType_Gnd_DOUBLE=5
  • NumNodesOfType_Gnd_DUMMY=4
  • NumNodesOfType_Gnd_INPUT=9
  • NumNodesOfType_Gnd_OMUX=6
  • NumNodesOfType_Gnd_OUTPUT=4
  • NumNodesOfType_Gnd_PREBXBY=4
  • NumNodesOfType_Vcc_CNTRLPIN=6
  • NumNodesOfType_Vcc_DUMMY=4
  • NumNodesOfType_Vcc_INPUT=9
  • NumNodesOfType_Vcc_PREBXBY=5
  • NumNodesOfType_Vcc_VCCOUT=8
 SiteStatistics
  • IOB-DIFFM=6
  • IOB-DIFFS=4
  • SLICEL-SLICEM=68
 		SiteSummary
  • BUFGMUX=5
  • BUFGMUX_GCLKMUX=5
  • BUFGMUX_GCLK_BUFFER=5
  • IOB=11
  • IOB_INBUF=5
  • IOB_OUTBUF=6
  • IOB_PAD=11
  • SLICEL=124
  • SLICEL_C1VDD=2
  • SLICEL_CYMUXF=40
  • SLICEL_CYMUXG=36
  • SLICEL_F=106
  • SLICEL_F5MUX=4
  • SLICEL_FFX=56
  • SLICEL_FFY=66
  • SLICEL_G=111
  • SLICEL_GNDF=8
  • SLICEL_GNDG=8
  • SLICEL_XORF=20
  • SLICEL_XORG=20
  • SLICEM=1
  • SLICEM_F=1
  • SLICEM_FFX=1
  • SLICEM_FFY=1
  • SLICEM_G=1
  • SLICEM_WSGEN=1
 
Configuration Data
BUFGMUX
  • S=[S_INV:5] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:5]
  • S=[S_INV:5] [S:0]
 IOB
  • O1=[O1_INV:0] [O1:6]
  • T1=[T1_INV:0] [T1:1]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:6]
  • TRI=[TRI_INV:0] [TRI:1]
 IOB_PAD
  • DRIVEATTRBOX=[12:6]
  • IOATTRBOX=[LVTTL:11]
  • SLEW=[SLOW:6]
 SLICEL
  • BX=[BX_INV:1] [BX:23]
  • BY=[BY:15] [BY_INV:2]
  • CE=[CE:42] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:32]
  • CLK=[CLK:51] [CLK_INV:17]
  • SR=[SR:16] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:40] [0_INV:0]
  • 1=[1_INV:0] [1:40]
 SLICEL_CYMUXG
  • 0=[0:36] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:4] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:36] [CE_INV:0]
  • CK=[CK:41] [CK_INV:15]
  • D=[D:55] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:56]
  • FFX_SR_ATTR=[SRLOW:56]
  • LATCH_OR_FF=[FF:56]
  • SR=[SR:13] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:43] [SYNC:13]
 SLICEL_FFY
  • CE=[CE:41] [CE_INV:0]
  • CK=[CK:49] [CK_INV:17]
  • D=[D:64] [D_INV:2]
  • FFY_INIT_ATTR=[INIT0:66]
  • FFY_SR_ATTR=[SRLOW:66]
  • LATCH_OR_FF=[FF:66]
  • SR=[SR:15] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:52] [SYNC:14]
 SLICEL_XORF
  • 1=[1_INV:0] [1:20]
 SLICEM
  • BX=[BX_INV:0] [BX:1]
  • BY=[BY:1] [BY_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
 SLICEM_F
  • DI=[DI:1] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
 SLICEM_FFX
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1]
  • FFX_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
 SLICEM_FFY
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:1]
  • FFY_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
 SLICEM_G
  • DI=[DI:1] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
 SLICEM_WSGEN
  • CK=[CK:1] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:1]
  • WE=[WE_INV:0] [WE:1]
 
Pin Data
BUFGMUX
  • I0=5
  • O=5
  • S=5
 BUFGMUX_GCLKMUX
  • I0=5
  • OUT=5
  • S=5
 BUFGMUX_GCLK_BUFFER
  • IN=5
  • OUT=5
 IOB
  • I=5
  • O1=6
  • PAD=11
  • T1=1
 IOB_INBUF
  • IN=5
  • OUT=5
 IOB_OUTBUF
  • IN=6
  • OUT=6
  • TRI=1
 IOB_PAD
  • PAD=11
 SLICEL
  • BX=24
  • BY=17
  • CE=42
  • CIN=32
  • CLK=68
  • COUT=36
  • F1=104
  • F2=92
  • F3=50
  • F4=30
  • G1=109
  • G2=97
  • G3=50
  • G4=32
  • SR=16
  • X=38
  • XQ=56
  • Y=34
  • YQ=66
 SLICEL_C1VDD
  • 1=2
 SLICEL_CYMUXF
  • 0=40
  • 1=40
  • OUT=40
  • S0=40
 SLICEL_CYMUXG
  • 0=36
  • 1=36
  • OUT=36
  • S0=36
 SLICEL_F
  • A1=100
  • A2=92
  • A3=50
  • A4=30
  • D=106
 SLICEL_F5MUX
  • F=4
  • G=4
  • OUT=4
  • S0=4
 SLICEL_FFX
  • CE=36
  • CK=56
  • D=56
  • Q=56
  • SR=13
 SLICEL_FFY
  • CE=41
  • CK=66
  • D=66
  • Q=66
  • SR=15
 SLICEL_G
  • A1=101
  • A2=97
  • A3=50
  • A4=32
  • D=111
 SLICEL_GNDF
  • 0=8
 SLICEL_GNDG
  • 0=8
 SLICEL_XORF
  • 0=20
  • 1=20
  • O=20
 SLICEL_XORG
  • 0=20
  • 1=20
  • O=20
 SLICEM
  • BX=1
  • BY=1
  • CLK=1
  • F1=1
  • F2=1
  • F3=1
  • F4=1
  • G1=1
  • G2=1
  • G3=1
  • G4=1
  • SR=1
  • XQ=1
  • YQ=1
 SLICEM_F
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
  • DI=1
  • WS=1
 SLICEM_FFX
  • CK=1
  • D=1
  • Q=1
 SLICEM_FFY
  • CK=1
  • D=1
  • Q=1
 SLICEM_G
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
  • DI=1
  • WS=1
 SLICEM_WSGEN
  • CK=1
  • WE=1
  • WSF=1
  • WSG=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 11 9 0 0 0 0 0
bitgen 34 34 0 0 0 0 0
map 43 40 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 46 46 0 0 0 0 0
par 40 35 2 0 0 0 0
trce 34 34 0 0 0 0 0
xst 135 132 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/sse_db_obsolete_symbols.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=Schematic
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-04-22T11:17:28 PROP_intWbtProjectID=5A4CD53EDB914E4F8C287B80FCD973BF
PROP_intWbtProjectIteration=9 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_ibiswriterOutputFile=AsteroidsClock PROP_DevDevice=xc3s400
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=tq144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL PROP_netgenPostMapSimModelName=AsteroidsClock_map.vhd
PROP_netgenPostParSimModelName=AsteroidsClock_timesim.vhd PROP_netgenPostSynthesisSimModelName=AsteroidsClock_synthesis.vhd
PROP_netgenPostXlateSimModelName=AsteroidsClock_translate.vhd PROP_netgenRenameTopLevEntTo=AsteroidsClock
FILE_SCHEMATIC=5 FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=129 NGDBUILD_NUM_AND2B1=128 NGDBUILD_NUM_AND3=3 NGDBUILD_NUM_AND3B1=4
NGDBUILD_NUM_AND3B2=1 NGDBUILD_NUM_AND4=1 NGDBUILD_NUM_AND4B1=3 NGDBUILD_NUM_AND4B2=3
NGDBUILD_NUM_AND4B3=1 NGDBUILD_NUM_BUF=1 NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_BUFGP=3
NGDBUILD_NUM_FD=26 NGDBUILD_NUM_FDC=1 NGDBUILD_NUM_FDCE=304 NGDBUILD_NUM_FDE=25
NGDBUILD_NUM_FDR=7 NGDBUILD_NUM_FDRE=20 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=18 NGDBUILD_NUM_LUT2=57 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=39 NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT4=48
NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_LUT4_L=3 NGDBUILD_NUM_MUXCY=76 NGDBUILD_NUM_MUXF5=4
NGDBUILD_NUM_OBUF=5 NGDBUILD_NUM_OBUFT=1 NGDBUILD_NUM_OR2=138 NGDBUILD_NUM_SRL16=2
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=40
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=129 NGDBUILD_NUM_AND2B1=128 NGDBUILD_NUM_AND3=3 NGDBUILD_NUM_AND3B1=4
NGDBUILD_NUM_AND3B2=1 NGDBUILD_NUM_AND4=1 NGDBUILD_NUM_AND4B1=3 NGDBUILD_NUM_AND4B2=3
NGDBUILD_NUM_AND4B3=1 NGDBUILD_NUM_BUF=1 NGDBUILD_NUM_BUFG=5 NGDBUILD_NUM_FD=26
NGDBUILD_NUM_FDC=1 NGDBUILD_NUM_FDCE=304 NGDBUILD_NUM_FDE=25 NGDBUILD_NUM_FDR=7
NGDBUILD_NUM_FDRE=20 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=3
NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=18 NGDBUILD_NUM_LUT2=57 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=39 NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT4=48
NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_LUT4_L=3 NGDBUILD_NUM_MUXCY=76 NGDBUILD_NUM_MUXF5=4
NGDBUILD_NUM_OBUF=5 NGDBUILD_NUM_OBUFT=1 NGDBUILD_NUM_OR2=138 NGDBUILD_NUM_SRLC16E=2
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=40
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5