| Project Statistics |
| PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Enable_Message_Filtering=false |
| PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
| PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
| PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
| PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=Schematic |
| PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2016-04-22T11:17:28 |
PROP_intWbtProjectID=5A4CD53EDB914E4F8C287B80FCD973BF |
| PROP_intWbtProjectIteration=20 |
PROP_intWorkingDirLocWRTProjDir=Same |
| PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
| PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
| PROP_ibiswriterOutputFile=AsteroidsClock |
PROP_DevDevice=xc3s400 |
| PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=tq144 |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
| PROP_PreferredLanguage=VHDL |
PROP_netgenPostMapSimModelName=AsteroidsClock_map.vhd |
| PROP_netgenPostParSimModelName=AsteroidsClock_timesim.vhd |
PROP_netgenPostSynthesisSimModelName=AsteroidsClock_synthesis.vhd |
| PROP_netgenPostXlateSimModelName=AsteroidsClock_translate.vhd |
PROP_netgenRenameTopLevEntTo=AsteroidsClock |
| FILE_SCHEMATIC=5 |
FILE_UCF=1 |
| FILE_VHDL=2 |