----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Carsten Meyer
-- 
-- Create Date:  17:17:17 04/27/2008 
-- Design Name: 
-- Module Name:  MPX3_XOR - Behavioral 
-- Project Name: ct-Lab AsteroidsClock
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity raster_count is
	Port ( SYSCLK:	in  STD_LOGIC;
				 DAC_XY: 	out STD_LOGIC_VECTOR (11 downto 0);
				 DAC_Z: 	out  STD_LOGIC_VECTOR (2 downto 0);  -- Asteroids
				 DAC_SEL: out  STD_LOGIC;
				 DAC_WR: 	out  STD_LOGIC 
			);
			
end raster_count;

architecture behavioral of raster_count is

	signal count_x, count_y : std_logic_vector (15 downto 0) :=x"0000";
	signal clk_int : Integer Range 0 to 63 := 0;
	signal clk_int_tick, dac_sel_int, vid_z : std_logic := '0';

begin

prescaler: process (SYSCLK)
begin
	if rising_edge(SYSCLK) then
	  clk_int_tick <= '0';
		clk_int <= clk_int + 1;
		if clk_int = 15 then
			clk_int <=	0;	
			clk_int_tick <= '1';
		end if;
	end if;
end process;

DAC_Z <= vid_z & vid_z & vid_z;
		
raster_scan: process (SYSCLK)
begin
	if rising_edge(SYSCLK) then
		DAC_WR <= '1';
		DAC_XY <= not (count_x(7 downto 0) & "0000");	-- 512 pixel Auflösung max.
		DAC_SEL <= '0';
		dac_sel_int <= '0';
		if clk_int_tick = '1' then
			count_x <= count_x + 1;		
			if count_x = 511 then
				DAC_XY <= (count_y(7 downto 0) & "0000");	-- 512 pixel Auflösung max.
				DAC_SEL <= '1';
				count_x <= (others => '0');
				count_y <= count_y + 1;
				if count_y = 511 then
					count_y <= (others => '0');
				end if;
			end if;
			DAC_WR <= '0';
		end if;
		
		vid_z <= (count_x(3) xor count_y(3));

		
	end if;
end process;

end Behavioral;