----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Carsten Meyer
-- 
-- Create Date:  17:17:17 04/27/2008 
-- Design Name: 
-- Module Name:  MPX3_XOR - Behavioral 
-- Project Name: ct-Lab AsteroidsClock
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sel_zmod is
    Port ( Q : out STD_LOGIC_VECTOR (2 downto 0);
           ASTEROIDS_Z : in  STD_LOGIC_VECTOR (3 downto 0);  -- Asteroids
           CLOCK_Z_N : in  STD_LOGIC;  -- ScopeClock
           SEL : in  STD_LOGIC;
			     CLK_100HZ : in  STD_LOGIC;
           BLINK_2HZ: out  STD_LOGIC 
				);
end sel_zmod;

architecture Behavioral of sel_zmod is

	signal clock_inv, blink_int: std_logic;
	signal rnd : std_logic_vector (15 downto 0) :=x"05A0";
	signal blink : std_logic_vector (4 downto 0) := (others => '0');

begin

clock_inv <= not CLOCK_Z_N;
blink_int <= blink(2) xor rnd(0) when ASTEROIDS_Z >= "1110" else ASTEROIDS_Z(1);

Q <= '0' & clock_inv & clock_inv when SEL = '1' else ASTEROIDS_Z(3 downto 2) & blink_int;
BLINK_2HZ <= blink(4);

set_noise: process (CLK_100HZ)
begin
	if rising_edge(CLK_100HZ) then
		-- Zufallsgenerator per 16-Bit-LFSR
		rnd(15 downto 1) <= rnd(14 downto 0) ;
		rnd(0) <= not(rnd(15) XOR rnd(14) XOR rnd(13) XOR rnd(4));
		blink <= blink +1;
	end if;
end process;

end Behavioral;