"E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1857: Unconnected output port 'SPIQ2' of component 'CTLAB_SPI_MUSER_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1857: Unconnected output port 'SPIQ3' of component 'CTLAB_SPI_MUSER_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D1' of component 'D3_8E_MXILINX_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D2' of component 'D3_8E_MXILINX_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D3' of component 'D3_8E_MXILINX_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D4' of component 'D3_8E_MXILINX_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D5' of component 'D3_8E_MXILINX_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D6' of component 'D3_8E_MXILINX_RasterScan'. "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D7' of component 'D3_8E_MXILINX_RasterScan'. Register <dac_sel_int> in unit <raster_count> has a constant value of 0 during circuit operation. The register is replaced by logic. Signal <dac_sel_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <XLXN_130> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_210_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_208_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_206_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_205_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <Q3L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q3H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q2L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q2H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q1L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q1H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q0L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Q0H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <REGSEL<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <REGSEL<3:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <XLXI_312_Reset_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_228_3_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_228_2_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_228_1_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_228_0_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <XLXI_183_SPID2_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000. Signal <XLXI_183_SPID1_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000. Signal <XLXI_183_SPID0_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000. Signal <CONFIG<31:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <CONFIG<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<31:29>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<27:25>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<23:21>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<19:17>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<15:13>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<11:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <BUTTON<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ADJUST<7:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ADJUST<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ADJUST<2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ADJUST<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. The FF/Latch <DAC_XY_0> in Unit <XLXI_344> is equivalent to the following 3 FFs/Latches, which will be removed : <DAC_XY_1> <DAC_XY_2> <DAC_XY_3> The FF/Latch <DAC_XY_0> in Unit <raster_count> is equivalent to the following 3 FFs/Latches, which will be removed : <DAC_XY_1> <DAC_XY_2> <DAC_XY_3>