--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 14.7
--  \   \         Application : sch2hdl
--  /   /         Filename : SPI32_OUT.vhf
-- /___/   /\     Timestamp : 04/27/2016 13:05:06
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl E:/Dropbox/CTLAB-RasterScan/main/SPI32_OUT.vhf -w E:/Dropbox/CTLAB-RasterScan/main/source/SPI32_OUT.sch
--Design Name: SPI32_OUT
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M2_1E_MXILINX_SPI32_OUT is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          E  : in    std_logic; 
          S0 : in    std_logic; 
          O  : out   std_logic);
end M2_1E_MXILINX_SPI32_OUT;

architecture BEHAVIORAL of M2_1E_MXILINX_SPI32_OUT is
   attribute BOX_TYPE   : string ;
   signal M0 : std_logic;
   signal M1 : std_logic;
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component AND3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
begin
   I_36_30 : AND3
      port map (I0=>D1,
                I1=>E,
                I2=>S0,
                O=>M1);
   
   I_36_31 : AND3B1
      port map (I0=>S0,
                I1=>E,
                I2=>D0,
                O=>M0);
   
   I_36_38 : OR2
      port map (I0=>M1,
                I1=>M0,
                O=>O);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M4_1E_MXILINX_SPI32_OUT is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          D2 : in    std_logic; 
          D3 : in    std_logic; 
          E  : in    std_logic; 
          S0 : in    std_logic; 
          S1 : in    std_logic; 
          O  : out   std_logic);
end M4_1E_MXILINX_SPI32_OUT;

architecture BEHAVIORAL of M4_1E_MXILINX_SPI32_OUT is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal M01 : std_logic;
   signal M23 : std_logic;
   component M2_1E_MXILINX_SPI32_OUT
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             E  : in    std_logic; 
             S0 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   component MUXF5
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             S  : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of MUXF5 : component is "BLACK_BOX";
   
   attribute HU_SET of I_M01 : label is "I_M01_42";
   attribute HU_SET of I_M23 : label is "I_M23_41";
begin
   I_M01 : M2_1E_MXILINX_SPI32_OUT
      port map (D0=>D0,
                D1=>D1,
                E=>E,
                S0=>S0,
                O=>M01);
   
   I_M23 : M2_1E_MXILINX_SPI32_OUT
      port map (D0=>D2,
                D1=>D3,
                E=>E,
                S0=>S0,
                O=>M23);
   
   I_O : MUXF5
      port map (I0=>M01,
                I1=>M23,
                S=>S1,
                O=>O);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M2_1_MXILINX_SPI32_OUT is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          S0 : in    std_logic; 
          O  : out   std_logic);
end M2_1_MXILINX_SPI32_OUT;

architecture BEHAVIORAL of M2_1_MXILINX_SPI32_OUT is
   attribute BOX_TYPE   : string ;
   signal M0 : std_logic;
   signal M1 : std_logic;
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
begin
   I_36_7 : AND2B1
      port map (I0=>S0,
                I1=>D0,
                O=>M0);
   
   I_36_8 : OR2
      port map (I0=>M1,
                I1=>M0,
                O=>O);
   
   I_36_9 : AND2
      port map (I0=>D1,
                I1=>S0,
                O=>M1);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR16CLE_MXILINX_SPI32_OUT is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (15 downto 0); 
          L   : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (15 downto 0));
end SR16CLE_MXILINX_SPI32_OUT;

architecture BEHAVIORAL of SR16CLE_MXILINX_SPI32_OUT is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal L_OR_CE : std_logic;
   signal MD0     : std_logic;
   signal MD1     : std_logic;
   signal MD2     : std_logic;
   signal MD3     : std_logic;
   signal MD4     : std_logic;
   signal MD5     : std_logic;
   signal MD6     : std_logic;
   signal MD7     : std_logic;
   signal MD8     : std_logic;
   signal MD9     : std_logic;
   signal MD10    : std_logic;
   signal MD11    : std_logic;
   signal MD12    : std_logic;
   signal MD13    : std_logic;
   signal MD14    : std_logic;
   signal MD15    : std_logic;
   signal Q_DUMMY : std_logic_vector (15 downto 0);
   component M2_1_MXILINX_SPI32_OUT
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             S0 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   attribute HU_SET of I_MQ0 : label is "I_MQ0_43";
   attribute HU_SET of I_MQ1 : label is "I_MQ1_44";
   attribute HU_SET of I_MQ2 : label is "I_MQ2_45";
   attribute HU_SET of I_MQ3 : label is "I_MQ3_46";
   attribute HU_SET of I_MQ4 : label is "I_MQ4_58";
   attribute HU_SET of I_MQ5 : label is "I_MQ5_57";
   attribute HU_SET of I_MQ6 : label is "I_MQ6_56";
   attribute HU_SET of I_MQ7 : label is "I_MQ7_55";
   attribute HU_SET of I_MQ8 : label is "I_MQ8_47";
   attribute HU_SET of I_MQ9 : label is "I_MQ9_48";
   attribute HU_SET of I_MQ10 : label is "I_MQ10_50";
   attribute HU_SET of I_MQ11 : label is "I_MQ11_49";
   attribute HU_SET of I_MQ12 : label is "I_MQ12_54";
   attribute HU_SET of I_MQ13 : label is "I_MQ13_53";
   attribute HU_SET of I_MQ14 : label is "I_MQ14_51";
   attribute HU_SET of I_MQ15 : label is "I_MQ15_52";
begin
   Q(15 downto 0) <= Q_DUMMY(15 downto 0);
   I_MQ0 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>SLI,
                D1=>D(0),
                S0=>L,
                O=>MD0);
   
   I_MQ1 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(0),
                D1=>D(1),
                S0=>L,
                O=>MD1);
   
   I_MQ2 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(1),
                D1=>D(2),
                S0=>L,
                O=>MD2);
   
   I_MQ3 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(2),
                D1=>D(3),
                S0=>L,
                O=>MD3);
   
   I_MQ4 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(3),
                D1=>D(4),
                S0=>L,
                O=>MD4);
   
   I_MQ5 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(4),
                D1=>D(5),
                S0=>L,
                O=>MD5);
   
   I_MQ6 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(5),
                D1=>D(6),
                S0=>L,
                O=>MD6);
   
   I_MQ7 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(6),
                D1=>D(7),
                S0=>L,
                O=>MD7);
   
   I_MQ8 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(7),
                D1=>D(8),
                S0=>L,
                O=>MD8);
   
   I_MQ9 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(8),
                D1=>D(9),
                S0=>L,
                O=>MD9);
   
   I_MQ10 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(9),
                D1=>D(10),
                S0=>L,
                O=>MD10);
   
   I_MQ11 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(10),
                D1=>D(11),
                S0=>L,
                O=>MD11);
   
   I_MQ12 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(11),
                D1=>D(12),
                S0=>L,
                O=>MD12);
   
   I_MQ13 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(12),
                D1=>D(13),
                S0=>L,
                O=>MD13);
   
   I_MQ14 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(13),
                D1=>D(14),
                S0=>L,
                O=>MD14);
   
   I_MQ15 : M2_1_MXILINX_SPI32_OUT
      port map (D0=>Q_DUMMY(14),
                D1=>D(15),
                S0=>L,
                O=>MD15);
   
   I_Q0 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD0,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD1,
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD2,
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD3,
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD4,
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD5,
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD6,
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD7,
                Q=>Q_DUMMY(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD8,
                Q=>Q_DUMMY(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD9,
                Q=>Q_DUMMY(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD10,
                Q=>Q_DUMMY(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD11,
                Q=>Q_DUMMY(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD12,
                Q=>Q_DUMMY(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD13,
                Q=>Q_DUMMY(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD14,
                Q=>Q_DUMMY(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD15,
                Q=>Q_DUMMY(15));
   
   I_36_67 : OR2
      port map (I0=>L,
                I1=>CE,
                O=>L_OR_CE);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI32_OUT is
   port ( A0         : in    std_logic; 
          A1         : in    std_logic; 
          DATA0      : in    std_logic_vector (31 downto 0); 
          DATA1      : in    std_logic_vector (31 downto 0); 
          DATA2      : in    std_logic_vector (31 downto 0); 
          DATA3      : in    std_logic_vector (31 downto 0); 
          ENABLE     : in    std_logic; 
          SPI_CLK    : in    std_logic; 
          SPI_SSDATA : in    std_logic; 
          SPI_MISO   : out   std_logic);
end SPI32_OUT;

architecture BEHAVIORAL of SPI32_OUT is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal Q0H                     : std_logic_vector (15 downto 0);
   signal Q0L                     : std_logic_vector (15 downto 0);
   signal Q1H                     : std_logic_vector (15 downto 0);
   signal Q1L                     : std_logic_vector (15 downto 0);
   signal Q2H                     : std_logic_vector (15 downto 0);
   signal Q2L                     : std_logic_vector (15 downto 0);
   signal Q3H                     : std_logic_vector (15 downto 0);
   signal Q3L                     : std_logic_vector (15 downto 0);
   signal SPI_CLKINV              : std_logic;
   signal SSDAT                   : std_logic;
   signal XLXN_244                : std_logic;
   signal XLXN_284                : std_logic;
   signal XLXN_291                : std_logic;
   signal XLXN_331                : std_logic;
   signal XLXI_205_SLI_openSignal : std_logic;
   signal XLXI_206_SLI_openSignal : std_logic;
   signal XLXI_208_SLI_openSignal : std_logic;
   signal XLXI_210_SLI_openSignal : std_logic;
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component FDC
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDC : component is "BLACK_BOX";
   
   component SR16CLE_MXILINX_SPI32_OUT
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (15 downto 0); 
             L   : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component M4_1E_MXILINX_SPI32_OUT
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             D2 : in    std_logic; 
             D3 : in    std_logic; 
             E  : in    std_logic; 
             S0 : in    std_logic; 
             S1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_203 : label is "XLXI_203_59";
   attribute HU_SET of XLXI_204 : label is "XLXI_204_60";
   attribute HU_SET of XLXI_205 : label is "XLXI_205_61";
   attribute HU_SET of XLXI_206 : label is "XLXI_206_62";
   attribute HU_SET of XLXI_208 : label is "XLXI_208_63";
   attribute HU_SET of XLXI_209 : label is "XLXI_209_64";
   attribute HU_SET of XLXI_210 : label is "XLXI_210_65";
   attribute HU_SET of XLXI_211 : label is "XLXI_211_66";
   attribute HU_SET of XLXI_212 : label is "XLXI_212_67";
begin
   XLXI_4 : GND
      port map (G=>XLXN_244);
   
   XLXI_119 : INV
      port map (I=>SPI_SSDATA,
                O=>SSDAT);
   
   XLXI_199 : FDC
      port map (C=>SPI_CLKINV,
                CLR=>SPI_SSDATA,
                D=>SSDAT,
                Q=>XLXN_284);
   
   XLXI_200 : INV
      port map (I=>XLXN_284,
                O=>XLXN_331);
   
   XLXI_203 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA0(31 downto 16),
                L=>XLXN_331,
                SLI=>Q0L(15),
                Q(15 downto 0)=>Q0H(15 downto 0));
   
   XLXI_204 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA1(31 downto 16),
                L=>XLXN_331,
                SLI=>Q1L(15),
                Q(15 downto 0)=>Q1H(15 downto 0));
   
   XLXI_205 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA0(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_205_SLI_openSignal,
                Q(15 downto 0)=>Q0L(15 downto 0));
   
   XLXI_206 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA1(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_206_SLI_openSignal,
                Q(15 downto 0)=>Q1L(15 downto 0));
   
   XLXI_207 : AND2
      port map (I0=>SSDAT,
                I1=>ENABLE,
                O=>XLXN_291);
   
   XLXI_208 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA2(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_208_SLI_openSignal,
                Q(15 downto 0)=>Q2L(15 downto 0));
   
   XLXI_209 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA2(31 downto 16),
                L=>XLXN_331,
                SLI=>Q2L(15),
                Q(15 downto 0)=>Q2H(15 downto 0));
   
   XLXI_210 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA3(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_210_SLI_openSignal,
                Q(15 downto 0)=>Q3L(15 downto 0));
   
   XLXI_211 : SR16CLE_MXILINX_SPI32_OUT
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA3(31 downto 16),
                L=>XLXN_331,
                SLI=>Q3L(15),
                Q(15 downto 0)=>Q3H(15 downto 0));
   
   XLXI_212 : M4_1E_MXILINX_SPI32_OUT
      port map (D0=>Q0H(15),
                D1=>Q1H(15),
                D2=>Q2H(15),
                D3=>Q3H(15),
                E=>XLXN_291,
                S0=>A0,
                S1=>A1,
                O=>SPI_MISO);
   
   XLXI_214 : INV
      port map (I=>SPI_CLK,
                O=>SPI_CLKINV);
   
end BEHAVIORAL;