Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Reading design: RasterScan.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "RasterScan.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "RasterScan"
Output Format                      : NGC
Target Device                      : xc3s400-4-tq144

---- Source Options
Top Module Name                    : RasterScan
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/source/Teiler50.vhd" in Library work.
Architecture behavioral of Entity teiler50t is up to date.
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/source/raster_count.vhd" in Library work.
Entity <raster_count> compiled.
Entity <raster_count> (Architecture <behavioral>) compiled.
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" in Library work.
Architecture behavioral of Entity d2_4e_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity fd16ce_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity sr16ce_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity spi32_in_muser_rasterscan is up to date.
Architecture behavioral of Entity d3_8e_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity fd8ce_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity sr8ce_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity spi8reg_in_muser_rasterscan is up to date.
Architecture behavioral of Entity m2_1e_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity m4_1e_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity m2_1_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity sr16cle_mxilinx_rasterscan is up to date.
Architecture behavioral of Entity spi32_out_muser_rasterscan is up to date.
Architecture behavioral of Entity ctlab_spi_muser_rasterscan is up to date.
Architecture behavioral of Entity rasterscan is up to date.
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/CTLAB_SPI.vhf" in Library work.
Architecture behavioral of Entity d2_4e_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity fd16ce_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity sr16ce_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity spi32_in_muser_ctlab_spi is up to date.
Architecture behavioral of Entity d3_8e_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity fd8ce_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity sr8ce_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity spi8reg_in_muser_ctlab_spi is up to date.
Architecture behavioral of Entity m2_1e_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity m4_1e_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity m2_1_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity sr16cle_mxilinx_ctlab_spi is up to date.
Architecture behavioral of Entity spi32_out_muser_ctlab_spi is up to date.
Architecture behavioral of Entity ctlab_spi is up to date.
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/SPI32_IN.vhf" in Library work.
Architecture behavioral of Entity d2_4e_mxilinx_spi32_in is up to date.
Architecture behavioral of Entity fd16ce_mxilinx_spi32_in is up to date.
Architecture behavioral of Entity sr16ce_mxilinx_spi32_in is up to date.
Architecture behavioral of Entity spi32_in is up to date.
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/SPI32_OUT.vhf" in Library work.
Architecture behavioral of Entity m2_1e_mxilinx_spi32_out is up to date.
Architecture behavioral of Entity m4_1e_mxilinx_spi32_out is up to date.
Architecture behavioral of Entity m2_1_mxilinx_spi32_out is up to date.
Architecture behavioral of Entity sr16cle_mxilinx_spi32_out is up to date.
Architecture behavioral of Entity spi32_out is up to date.
Compiling vhdl file "E:/Dropbox/CTLAB-RasterScan/main/SPI8REG_IN.vhf" in Library work.
Architecture behavioral of Entity fd8ce_mxilinx_spi8reg_in is up to date.
Architecture behavioral of Entity sr8ce_mxilinx_spi8reg_in is up to date.
Architecture behavioral of Entity spi8reg_in is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <CTLAB_SPI_MUSER_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <Teiler50T> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <raster_count> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SPI32_OUT_MUSER_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SPI8REG_IN_MUSER_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SPI32_IN_MUSER_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <D3_8E_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SR16CLE_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <M4_1E_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SR8CE_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <FD8CE_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SR16CE_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <FD16CE_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <D2_4E_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <M2_1_MXILINX_RasterScan> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <M2_1E_MXILINX_RasterScan> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <RasterScan> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1857: Unconnected output port 'SPIQ2' of component 'CTLAB_SPI_MUSER_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1857: Unconnected output port 'SPIQ3' of component 'CTLAB_SPI_MUSER_RasterScan'.
Entity <RasterScan> analyzed. Unit <RasterScan> generated.

Analyzing Entity <CTLAB_SPI_MUSER_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "DRIVE =  12" for instance <XLXI_44> in unit <CTLAB_SPI_MUSER_RasterScan>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <XLXI_44> in unit <CTLAB_SPI_MUSER_RasterScan>.
    Set user-defined property "SLEW =  SLOW" for instance <XLXI_44> in unit <CTLAB_SPI_MUSER_RasterScan>.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D1' of component 'D3_8E_MXILINX_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D2' of component 'D3_8E_MXILINX_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D3' of component 'D3_8E_MXILINX_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D4' of component 'D3_8E_MXILINX_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D5' of component 'D3_8E_MXILINX_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D6' of component 'D3_8E_MXILINX_RasterScan'.
WARNING:Xst:753 - "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf" line 1744: Unconnected output port 'D7' of component 'D3_8E_MXILINX_RasterScan'.
    Set user-defined property "HU_SET =  XLXI_171_40" for instance <XLXI_171> in unit <CTLAB_SPI_MUSER_RasterScan>.
Entity <CTLAB_SPI_MUSER_RasterScan> analyzed. Unit <CTLAB_SPI_MUSER_RasterScan> generated.

Analyzing Entity <SPI32_OUT_MUSER_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <XLXI_199> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_203_31" for instance <XLXI_203> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_204_32" for instance <XLXI_204> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_205_33" for instance <XLXI_205> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_206_34" for instance <XLXI_206> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_208_35" for instance <XLXI_208> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_209_36" for instance <XLXI_209> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_210_37" for instance <XLXI_210> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_211_38" for instance <XLXI_211> in unit <SPI32_OUT_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_212_39" for instance <XLXI_212> in unit <SPI32_OUT_MUSER_RasterScan>.
Entity <SPI32_OUT_MUSER_RasterScan> analyzed. Unit <SPI32_OUT_MUSER_RasterScan> generated.

Analyzing Entity <SR16CLE_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  I_MQ0_15" for instance <I_MQ0> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ1_16" for instance <I_MQ1> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ2_17" for instance <I_MQ2> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ3_18" for instance <I_MQ3> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ4_30" for instance <I_MQ4> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ5_29" for instance <I_MQ5> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ6_28" for instance <I_MQ6> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ7_27" for instance <I_MQ7> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ8_19" for instance <I_MQ8> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ9_20" for instance <I_MQ9> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ10_22" for instance <I_MQ10> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ11_21" for instance <I_MQ11> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ12_26" for instance <I_MQ12> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ13_25" for instance <I_MQ13> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ14_23" for instance <I_MQ14> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_MQ15_24" for instance <I_MQ15> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q4> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q5> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q6> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q7> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q8> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q9> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q10> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q11> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q12> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q13> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q14> in unit <SR16CLE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q15> in unit <SR16CLE_MXILINX_RasterScan>.
Entity <SR16CLE_MXILINX_RasterScan> analyzed. Unit <SR16CLE_MXILINX_RasterScan> generated.

Analyzing Entity <M2_1_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
Entity <M2_1_MXILINX_RasterScan> analyzed. Unit <M2_1_MXILINX_RasterScan> generated.

Analyzing Entity <M4_1E_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  I_M01_14" for instance <I_M01> in unit <M4_1E_MXILINX_RasterScan>.
    Set user-defined property "HU_SET =  I_M23_13" for instance <I_M23> in unit <M4_1E_MXILINX_RasterScan>.
Entity <M4_1E_MXILINX_RasterScan> analyzed. Unit <M4_1E_MXILINX_RasterScan> generated.

Analyzing Entity <M2_1E_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
Entity <M2_1E_MXILINX_RasterScan> analyzed. Unit <M2_1E_MXILINX_RasterScan> generated.

Analyzing Entity <SPI8REG_IN_MUSER_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  XLXI_93_11" for instance <XLXI_93> in unit <SPI8REG_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_94_12" for instance <XLXI_94> in unit <SPI8REG_IN_MUSER_RasterScan>.
Entity <SPI8REG_IN_MUSER_RasterScan> analyzed. Unit <SPI8REG_IN_MUSER_RasterScan> generated.

Analyzing Entity <SR8CE_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q4> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q5> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q6> in unit <SR8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q7> in unit <SR8CE_MXILINX_RasterScan>.
Entity <SR8CE_MXILINX_RasterScan> analyzed. Unit <SR8CE_MXILINX_RasterScan> generated.

Analyzing Entity <FD8CE_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q4> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q5> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q6> in unit <FD8CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q7> in unit <FD8CE_MXILINX_RasterScan>.
Entity <FD8CE_MXILINX_RasterScan> analyzed. Unit <FD8CE_MXILINX_RasterScan> generated.

Analyzing Entity <SPI32_IN_MUSER_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  XLXI_2_0" for instance <XLXI_2> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_3_1" for instance <XLXI_3> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_88_2" for instance <XLXI_88> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_89_3" for instance <XLXI_89> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_96_10" for instance <XLXI_96> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_100_4" for instance <XLXI_100> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_101_5" for instance <XLXI_101> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_102_6" for instance <XLXI_102> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_103_7" for instance <XLXI_103> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_104_8" for instance <XLXI_104> in unit <SPI32_IN_MUSER_RasterScan>.
    Set user-defined property "HU_SET =  XLXI_105_9" for instance <XLXI_105> in unit <SPI32_IN_MUSER_RasterScan>.
Entity <SPI32_IN_MUSER_RasterScan> analyzed. Unit <SPI32_IN_MUSER_RasterScan> generated.

Analyzing Entity <SR16CE_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q4> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q5> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q6> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q7> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q8> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q9> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q10> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q11> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q12> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q13> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q14> in unit <SR16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q15> in unit <SR16CE_MXILINX_RasterScan>.
Entity <SR16CE_MXILINX_RasterScan> analyzed. Unit <SR16CE_MXILINX_RasterScan> generated.

Analyzing Entity <FD16CE_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q4> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q5> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q6> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q7> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q8> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q9> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q10> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q11> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q12> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q13> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q14> in unit <FD16CE_MXILINX_RasterScan>.
    Set user-defined property "INIT =  0" for instance <I_Q15> in unit <FD16CE_MXILINX_RasterScan>.
Entity <FD16CE_MXILINX_RasterScan> analyzed. Unit <FD16CE_MXILINX_RasterScan> generated.

Analyzing Entity <D2_4E_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
Entity <D2_4E_MXILINX_RasterScan> analyzed. Unit <D2_4E_MXILINX_RasterScan> generated.

Analyzing Entity <D3_8E_MXILINX_RasterScan> in library <work> (Architecture <behavioral>).
Entity <D3_8E_MXILINX_RasterScan> analyzed. Unit <D3_8E_MXILINX_RasterScan> generated.

Analyzing Entity <Teiler50T> in library <work> (Architecture <behavioral>).
Entity <Teiler50T> analyzed. Unit <Teiler50T> generated.

Analyzing Entity <raster_count> in library <work> (Architecture <behavioral>).
INFO:Xst:2679 - Register <dac_sel_int> in unit <raster_count> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <raster_count> analyzed. Unit <raster_count> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Teiler50T>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/source/Teiler50.vhd".
    Found finite state machine <FSM_0> for signal <var_zustand_vektor>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Q>.
    Found 20-bit register for signal <var_zaehler_vektor>.
    Found 20-bit adder for signal <var_zaehler_vektor$share0000> created at line 51.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  21 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <Teiler50T> synthesized.


Synthesizing Unit <raster_count>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/source/raster_count.vhd".
WARNING:Xst:646 - Signal <dac_sel_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <DAC_SEL>.
    Found 1-bit register for signal <DAC_WR>.
    Found 12-bit register for signal <DAC_XY>.
    Found 6-bit up counter for signal <clk_int>.
    Found 1-bit register for signal <clk_int_tick>.
    Found 16-bit up counter for signal <count_x>.
    Found 16-bit up counter for signal <count_y>.
    Found 1-bit register for signal <vid_z>.
    Found 1-bit xor2 for signal <vid_z$xor0000> created at line 73.
    Summary:
	inferred   3 Counter(s).
	inferred  16 D-type flip-flop(s).
Unit <raster_count> synthesized.


Synthesizing Unit <D3_8E_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <D3_8E_MXILINX_RasterScan> synthesized.


Synthesizing Unit <M2_1_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <M2_1_MXILINX_RasterScan> synthesized.


Synthesizing Unit <M2_1E_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <M2_1E_MXILINX_RasterScan> synthesized.


Synthesizing Unit <SR8CE_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <SR8CE_MXILINX_RasterScan> synthesized.


Synthesizing Unit <FD8CE_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <FD8CE_MXILINX_RasterScan> synthesized.


Synthesizing Unit <SR16CE_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <SR16CE_MXILINX_RasterScan> synthesized.


Synthesizing Unit <FD16CE_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <FD16CE_MXILINX_RasterScan> synthesized.


Synthesizing Unit <D2_4E_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <D2_4E_MXILINX_RasterScan> synthesized.


Synthesizing Unit <SPI8REG_IN_MUSER_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <SPI8REG_IN_MUSER_RasterScan> synthesized.


Synthesizing Unit <SPI32_IN_MUSER_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
WARNING:Xst:653 - Signal <XLXN_130> is used but never assigned. This sourceless signal will be automatically connected to value 0.
Unit <SPI32_IN_MUSER_RasterScan> synthesized.


Synthesizing Unit <SR16CLE_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <SR16CLE_MXILINX_RasterScan> synthesized.


Synthesizing Unit <M4_1E_MXILINX_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
Unit <M4_1E_MXILINX_RasterScan> synthesized.


Synthesizing Unit <SPI32_OUT_MUSER_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
WARNING:Xst:653 - Signal <XLXI_210_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_208_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_206_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_205_SLI_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <Q3L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q3H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q2L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q2H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q1L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q1H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q0L<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Q0H<14:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <SPI32_OUT_MUSER_RasterScan> synthesized.


Synthesizing Unit <CTLAB_SPI_MUSER_RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
WARNING:Xst:646 - Signal <REGSEL<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <REGSEL<3:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <CTLAB_SPI_MUSER_RasterScan> synthesized.


Synthesizing Unit <RasterScan>.
    Related source file is "E:/Dropbox/CTLAB-RasterScan/main/RasterScan.vhf".
WARNING:Xst:653 - Signal <XLXI_312_Reset_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_228_3_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_228_2_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_228_1_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_228_0_I_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <XLXI_183_SPID2_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <XLXI_183_SPID1_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <XLXI_183_SPID0_openSignal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:646 - Signal <CONFIG<31:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CONFIG<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<31:29>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<27:25>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<23:21>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<19:17>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<15:13>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<11:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BUTTON<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ADJUST<7:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ADJUST<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ADJUST<2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ADJUST<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <RasterScan> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 20-bit adder                                          : 1
# Counters                                             : 3
 16-bit up counter                                     : 2
 6-bit up counter                                      : 1
# Registers                                            : 7
 1-bit register                                        : 5
 12-bit register                                       : 1
 20-bit register                                       : 1
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <XLXI_312/var_zustand_vektor/FSM> on signal <var_zustand_vektor[1:1]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 00    | 0
 01    | 1
-------------------
INFO:Xst:2261 - The FF/Latch <DAC_XY_0> in Unit <XLXI_344> is equivalent to the following 3 FFs/Latches, which will be removed : <DAC_XY_1> <DAC_XY_2> <DAC_XY_3> 

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Adders/Subtractors                                   : 1
 20-bit adder                                          : 1
# Counters                                             : 3
 16-bit up counter                                     : 2
 6-bit up counter                                      : 1
# Registers                                            : 342
 Flip-Flops                                            : 342
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <DAC_XY_0> in Unit <raster_count> is equivalent to the following 3 FFs/Latches, which will be removed : <DAC_XY_1> <DAC_XY_2> <DAC_XY_3> 

Optimizing unit <RasterScan> ...

Optimizing unit <Teiler50T> ...

Optimizing unit <raster_count> ...

Optimizing unit <D3_8E_MXILINX_RasterScan> ...

Optimizing unit <M2_1_MXILINX_RasterScan> ...

Optimizing unit <M2_1E_MXILINX_RasterScan> ...

Optimizing unit <SR8CE_MXILINX_RasterScan> ...

Optimizing unit <FD8CE_MXILINX_RasterScan> ...

Optimizing unit <SR16CE_MXILINX_RasterScan> ...

Optimizing unit <FD16CE_MXILINX_RasterScan> ...

Optimizing unit <D2_4E_MXILINX_RasterScan> ...

Optimizing unit <SPI32_IN_MUSER_RasterScan> ...

Optimizing unit <SR16CLE_MXILINX_RasterScan> ...

Optimizing unit <M4_1E_MXILINX_RasterScan> ...

Optimizing unit <SPI32_OUT_MUSER_RasterScan> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block RasterScan, actual ratio is 6.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 378
 Flip-Flops                                            : 378

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : RasterScan.ngr
Top Level Output File Name         : RasterScan
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 32

Cell Usage :
# BELS                             : 667
#      AND2                        : 129
#      AND2B1                      : 128
#      AND3                        : 3
#      AND3B1                      : 4
#      AND3B2                      : 1
#      AND4                        : 1
#      AND4B1                      : 3
#      AND4B2                      : 3
#      AND4B3                      : 1
#      BUF                         : 5
#      GND                         : 1
#      INV                         : 20
#      LUT1                        : 50
#      LUT2                        : 2
#      LUT3                        : 14
#      LUT3_D                      : 1
#      LUT3_L                      : 2
#      LUT4                        : 42
#      LUT4_D                      : 3
#      LUT4_L                      : 1
#      MUXCY                       : 59
#      MUXF5                       : 3
#      OR2                         : 138
#      VCC                         : 1
#      XORCY                       : 52
# FlipFlops/Latches                : 378
#      FD                          : 10
#      FDC                         : 22
#      FDCE                        : 304
#      FDE                         : 1
#      FDR                         : 9
#      FDRE                        : 32
# Clock Buffers                    : 4
#      BUFG                        : 1
#      BUFGP                       : 3
# IO Buffers                       : 29
#      IBUF                        : 3
#      OBUF                        : 25
#      OBUFT                       : 1
# Others                           : 1
#      PULLUP                      : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400tq144-4 

 Number of Slices:                      189  out of   3584     5%  
 Number of Slice Flip Flops:            378  out of   7168     5%  
 Number of 4 input LUTs:                135  out of   7168     1%  
 Number of IOs:                          32
 Number of bonded IOBs:                  32  out of     97    32%  
 Number of GCLKs:                         4  out of      8    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
ClkIn                              | BUFGP                  | 73    |
F_SCK                              | BUFGP                  | 169   |
F_RS                               | BUFGP                  | 8     |
F_DS                               | IBUF+BUFG              | 128   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------+--------------------------------------+-------+
Control Signal                                       | Buffer(FF name)                      | Load  |
-----------------------------------------------------+--------------------------------------+-------+
XLXI_183/XLXI_168/XLXN_38(XLXI_183/XLXI_168/XLXI_4:G)| NONE(XLXI_183/XLXI_110/XLXI_203/I_Q0)| 325   |
F_DS                                                 | IBUF                                 | 1     |
-----------------------------------------------------+--------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.227ns (Maximum Frequency: 121.551MHz)
   Minimum input arrival time before clock: 5.813ns
   Maximum output required time after clock: 13.451ns
   Maximum combinational path delay: 13.599ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'ClkIn'
  Clock period: 8.227ns (frequency: 121.551MHz)
  Total number of paths / destination ports: 3167 / 143
-------------------------------------------------------------------------
Delay:               8.227ns (Levels of Logic = 8)
  Source:            XLXI_344/count_x_3 (FF)
  Destination:       XLXI_344/count_y_15 (FF)
  Source Clock:      ClkIn rising
  Destination Clock: ClkIn rising

  Data Path: XLXI_344/count_x_3 to XLXI_344/count_y_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             4   0.720   1.256  XLXI_344/count_x_3 (XLXI_344/count_x_3)
     LUT1:I0->O            1   0.551   0.000  XLXI_344/DAC_SEL_or0000_wg_cy<0>_rt (XLXI_344/DAC_SEL_or0000_wg_cy<0>_rt)
     MUXCY:S->O            1   0.500   0.000  XLXI_344/DAC_SEL_or0000_wg_cy<0> (XLXI_344/DAC_SEL_or0000_wg_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  XLXI_344/DAC_SEL_or0000_wg_cy<1> (XLXI_344/DAC_SEL_or0000_wg_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  XLXI_344/DAC_SEL_or0000_wg_cy<2> (XLXI_344/DAC_SEL_or0000_wg_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  XLXI_344/DAC_SEL_or0000_wg_cy<3> (XLXI_344/DAC_SEL_or0000_wg_cy<3>)
     MUXCY:CI->O          13   0.281   1.196  XLXI_344/DAC_SEL_or0000_wg_cy<4> (XLXI_344/DAC_SEL_or0000)
     LUT4:I3->O            1   0.551   0.000  XLXI_344/count_y_and0000_wg_lut<4> (XLXI_344/count_y_and0000_wg_lut<4>)
     MUXCY:S->O           16   0.717   1.237  XLXI_344/count_y_and0000_wg_cy<4> (XLXI_344/count_y_and0000)
     FDRE:R                    1.026          XLXI_344/count_y_0
    ----------------------------------------
    Total                      8.227ns (4.538ns logic, 3.689ns route)
                                       (55.2% logic, 44.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'F_SCK'
  Clock period: 8.161ns (frequency: 122.533MHz)
  Total number of paths / destination ports: 546 / 294
-------------------------------------------------------------------------
Delay:               8.161ns (Levels of Logic = 5)
  Source:            XLXI_183/XLXI_110/XLXI_199 (FF)
  Destination:       XLXI_183/XLXI_110/XLXI_203/I_Q0 (FF)
  Source Clock:      F_SCK falling
  Destination Clock: F_SCK falling

  Data Path: XLXI_183/XLXI_110/XLXI_199 to XLXI_183/XLXI_110/XLXI_203/I_Q0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.720   0.801  XLXI_183/XLXI_110/XLXI_199 (XLXI_183/XLXI_110/XLXN_284)
     INV:I->O            264   0.551   3.182  XLXI_183/XLXI_110/XLXI_200 (XLXI_183/XLXI_110/XLXN_331)
     begin scope: 'XLXI_183/XLXI_110/XLXI_211'
     begin scope: 'I_MQ15'
     AND2B1:I0->O          1   0.551   0.801  I_36_7 (M0)
     OR2:I1->O             1   0.551   0.801  I_36_8 (O)
     end scope: 'I_MQ15'
     FDCE:D                    0.203          I_Q15
    ----------------------------------------
    Total                      8.161ns (2.576ns logic, 5.585ns route)
                                       (31.6% logic, 68.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'F_SCK'
  Total number of paths / destination ports: 131 / 131
-------------------------------------------------------------------------
Offset:              5.813ns (Levels of Logic = 4)
  Source:            F_DS (PAD)
  Destination:       XLXI_183/XLXI_110/XLXI_203/I_Q0 (FF)
  Destination Clock: F_SCK falling

  Data Path: F_DS to XLXI_183/XLXI_110/XLXI_203/I_Q0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.821   0.917  F_DS_IBUF (F_DS_IBUF1)
     INV:I->O             10   0.551   1.134  XLXI_183/XLXI_110/XLXI_119 (XLXI_183/XLXI_110/SSDAT)
     begin scope: 'XLXI_183/XLXI_110/XLXI_211'
     OR2:I1->O            16   0.551   1.237  I_36_67 (L_OR_CE)
     FDCE:CE                   0.602          I_Q0
    ----------------------------------------
    Total                      5.813ns (2.525ns logic, 3.288ns route)
                                       (43.4% logic, 56.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'ClkIn'
  Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Offset:              7.281ns (Levels of Logic = 1)
  Source:            XLXI_344/DAC_XY_0 (FF)
  Destination:       DAC<3> (PAD)
  Source Clock:      ClkIn rising

  Data Path: XLXI_344/DAC_XY_0 to DAC<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.720   0.917  XLXI_344/DAC_XY_0 (XLXI_344/DAC_XY_0)
     OBUF:I->O                 5.644          DAC_3_OBUF (DAC<3>)
    ----------------------------------------
    Total                      7.281ns (6.364ns logic, 0.917ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'F_SCK'
  Total number of paths / destination ports: 4 / 1
-------------------------------------------------------------------------
Offset:              10.229ns (Levels of Logic = 7)
  Source:            XLXI_183/XLXI_110/XLXI_204/I_Q15 (FF)
  Destination:       F_MISO (PAD)
  Source Clock:      F_SCK falling

  Data Path: XLXI_183/XLXI_110/XLXI_204/I_Q15 to F_MISO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.720   0.801  I_Q15 (Q<15>)
     end scope: 'XLXI_183/XLXI_110/XLXI_204'
     begin scope: 'XLXI_183/XLXI_110/XLXI_212'
     begin scope: 'I_M01'
     AND3:I0->O            1   0.551   0.801  I_36_30 (M1)
     OR2:I0->O             1   0.551   0.000  I_36_38 (O)
     end scope: 'I_M01'
     MUXF5:I0->O           1   0.360   0.801  I_O (O)
     end scope: 'XLXI_183/XLXI_110/XLXI_212'
     OBUFT:I->O                5.644          XLXI_183/XLXI_44 (F_MISO)
    ----------------------------------------
    Total                     10.229ns (7.826ns logic, 2.403ns route)
                                       (76.5% logic, 23.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'F_RS'
  Total number of paths / destination ports: 17 / 1
-------------------------------------------------------------------------
Offset:              13.451ns (Levels of Logic = 10)
  Source:            XLXI_183/XLXI_168/XLXI_94/I_Q6 (FF)
  Destination:       F_MISO (PAD)
  Source Clock:      F_RS rising

  Data Path: XLXI_183/XLXI_168/XLXI_94/I_Q6 to F_MISO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             8   0.720   1.083  I_Q6 (Q<6>)
     end scope: 'XLXI_183/XLXI_168/XLXI_94'
     begin scope: 'XLXI_183/XLXI_171'
     AND4B3:I0->O          5   0.551   0.921  I_36_37 (D0)
     end scope: 'XLXI_183/XLXI_171'
     AND2:I1->O            4   0.551   0.917  XLXI_183/XLXI_110/XLXI_207 (XLXI_183/XLXI_110/XLXN_291)
     begin scope: 'XLXI_183/XLXI_110/XLXI_212'
     begin scope: 'I_M23'
     AND3:I1->O            1   0.551   0.801  I_36_30 (M1)
     OR2:I0->O             1   0.551   0.000  I_36_38 (O)
     end scope: 'I_M23'
     MUXF5:I1->O           1   0.360   0.801  I_O (O)
     end scope: 'XLXI_183/XLXI_110/XLXI_212'
     OBUFT:I->O                5.644          XLXI_183/XLXI_44 (F_MISO)
    ----------------------------------------
    Total                     13.451ns (8.928ns logic, 4.523ns route)
                                       (66.4% logic, 33.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 5 / 1
-------------------------------------------------------------------------
Delay:               13.599ns (Levels of Logic = 9)
  Source:            F_DS (PAD)
  Destination:       F_MISO (PAD)

  Data Path: F_DS to F_MISO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.821   0.917  F_DS_IBUF (F_DS_IBUF1)
     INV:I->O             10   0.551   1.134  XLXI_183/XLXI_110/XLXI_119 (XLXI_183/XLXI_110/SSDAT)
     AND2:I0->O            4   0.551   0.917  XLXI_183/XLXI_110/XLXI_207 (XLXI_183/XLXI_110/XLXN_291)
     begin scope: 'XLXI_183/XLXI_110/XLXI_212'
     begin scope: 'I_M23'
     AND3:I1->O            1   0.551   0.801  I_36_30 (M1)
     OR2:I0->O             1   0.551   0.000  I_36_38 (O)
     end scope: 'I_M23'
     MUXF5:I1->O           1   0.360   0.801  I_O (O)
     end scope: 'XLXI_183/XLXI_110/XLXI_212'
     OBUFT:I->O                5.644          XLXI_183/XLXI_44 (F_MISO)
    ----------------------------------------
    Total                     13.599ns (9.029ns logic, 4.570ns route)
                                       (66.4% logic, 33.6% route)

=========================================================================


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 14.34 secs
 
--> 

Total memory usage is 285988 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   47 (   0 filtered)
Number of infos    :    4 (   0 filtered)