--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 14.7
--  \   \         Application : sch2hdl
--  /   /         Filename : CTLAB_SPI.vhf
-- /___/   /\     Timestamp : 04/27/2016 13:05:11
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl E:/Dropbox/CTLAB-RasterScan/main/CTLAB_SPI.vhf -w E:/Dropbox/CTLAB-RasterScan/main/source/CTLAB_SPI.sch
--Design Name: CTLAB_SPI
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity D2_4E_MXILINX_CTLAB_SPI is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic);
end D2_4E_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of D2_4E_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component AND3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
   
   component AND3B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
   
begin
   I_36_30 : AND3
      port map (I0=>A1,
                I1=>A0,
                I2=>E,
                O=>D3);
   
   I_36_31 : AND3B1
      port map (I0=>A0,
                I1=>A1,
                I2=>E,
                O=>D2);
   
   I_36_32 : AND3B1
      port map (I0=>A1,
                I1=>A0,
                I2=>E,
                O=>D1);
   
   I_36_33 : AND3B2
      port map (I0=>A0,
                I1=>A1,
                I2=>E,
                O=>D0);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity FD16CE_MXILINX_CTLAB_SPI is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (15 downto 0); 
          Q   : out   std_logic_vector (15 downto 0));
end FD16CE_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of FD16CE_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(0),
                Q=>Q(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(1),
                Q=>Q(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(2),
                Q=>Q(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(3),
                Q=>Q(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(4),
                Q=>Q(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(5),
                Q=>Q(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(6),
                Q=>Q(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(7),
                Q=>Q(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(8),
                Q=>Q(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(9),
                Q=>Q(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(10),
                Q=>Q(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(11),
                Q=>Q(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(12),
                Q=>Q(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(13),
                Q=>Q(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(14),
                Q=>Q(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(15),
                Q=>Q(15));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR16CE_MXILINX_CTLAB_SPI is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (15 downto 0));
end SR16CE_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of SR16CE_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   signal Q_DUMMY : std_logic_vector (15 downto 0);
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   Q(15 downto 0) <= Q_DUMMY(15 downto 0);
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>SLI,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(0),
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(1),
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(2),
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(3),
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(4),
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(5),
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(6),
                Q=>Q_DUMMY(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(7),
                Q=>Q_DUMMY(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(8),
                Q=>Q_DUMMY(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(9),
                Q=>Q_DUMMY(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(10),
                Q=>Q_DUMMY(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(11),
                Q=>Q_DUMMY(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(12),
                Q=>Q_DUMMY(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(13),
                Q=>Q_DUMMY(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(14),
                Q=>Q_DUMMY(15));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI32_IN_MUSER_CTLAB_SPI is
   port ( A0         : in    std_logic; 
          A1         : in    std_logic; 
          ENABLE     : in    std_logic; 
          SPI_CLK    : in    std_logic; 
          SPI_MOSI   : in    std_logic; 
          SPI_SSDATA : in    std_logic; 
          DATA0      : out   std_logic_vector (31 downto 0); 
          DATA1      : out   std_logic_vector (31 downto 0); 
          DATA2      : out   std_logic_vector (31 downto 0); 
          DATA3      : out   std_logic_vector (31 downto 0));
end SPI32_IN_MUSER_CTLAB_SPI;

architecture BEHAVIORAL of SPI32_IN_MUSER_CTLAB_SPI is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal Sel0       : std_logic;
   signal Sel1       : std_logic;
   signal Sel2       : std_logic;
   signal Sel3       : std_logic;
   signal ShiftLSB   : std_logic_vector (15 downto 0);
   signal ShiftMSB   : std_logic_vector (15 downto 0);
   signal XLXN_38    : std_logic;
   signal XLXN_130   : std_logic;
   signal XLXN_151   : std_logic;
   component SR16CE_MXILINX_CTLAB_SPI
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
   
   component FD16CE_MXILINX_CTLAB_SPI
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (15 downto 0); 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   component D2_4E_MXILINX_CTLAB_SPI
      port ( A0 : in    std_logic; 
             A1 : in    std_logic; 
             E  : in    std_logic; 
             D0 : out   std_logic; 
             D1 : out   std_logic; 
             D2 : out   std_logic; 
             D3 : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_2 : label is "XLXI_2_81";
   attribute HU_SET of XLXI_3 : label is "XLXI_3_82";
   attribute HU_SET of XLXI_88 : label is "XLXI_88_83";
   attribute HU_SET of XLXI_89 : label is "XLXI_89_84";
   attribute HU_SET of XLXI_96 : label is "XLXI_96_91";
   attribute HU_SET of XLXI_100 : label is "XLXI_100_85";
   attribute HU_SET of XLXI_101 : label is "XLXI_101_86";
   attribute HU_SET of XLXI_102 : label is "XLXI_102_87";
   attribute HU_SET of XLXI_103 : label is "XLXI_103_88";
   attribute HU_SET of XLXI_104 : label is "XLXI_104_89";
   attribute HU_SET of XLXI_105 : label is "XLXI_105_90";
begin
   XLXI_2 : SR16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLK,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                SLI=>SPI_MOSI,
                Q(15 downto 0)=>ShiftLSB(15 downto 0));
   
   XLXI_3 : SR16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLK,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                SLI=>ShiftLSB(15),
                Q(15 downto 0)=>ShiftMSB(15 downto 0));
   
   XLXI_4 : GND
      port map (G=>XLXN_38);
   
   XLXI_85 : VCC
      port map (P=>XLXN_151);
   
   XLXI_88 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel0,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA0(15 downto 0));
   
   XLXI_89 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel0,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA0(31 downto 16));
   
   XLXI_96 : D2_4E_MXILINX_CTLAB_SPI
      port map (A0=>A0,
                A1=>A1,
                E=>ENABLE,
                D0=>Sel0,
                D1=>Sel1,
                D2=>Sel2,
                D3=>Sel3);
   
   XLXI_100 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel1,
                CLR=>XLXN_130,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA1(15 downto 0));
   
   XLXI_101 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel1,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA1(31 downto 16));
   
   XLXI_102 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel2,
                CLR=>XLXN_130,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA2(15 downto 0));
   
   XLXI_103 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel2,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA2(31 downto 16));
   
   XLXI_104 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel3,
                CLR=>XLXN_130,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA3(15 downto 0));
   
   XLXI_105 : FD16CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSDATA,
                CE=>Sel3,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA3(31 downto 16));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity D3_8E_MXILINX_CTLAB_SPI is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          A2 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic; 
          D4 : out   std_logic; 
          D5 : out   std_logic; 
          D6 : out   std_logic; 
          D7 : out   std_logic);
end D3_8E_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of D3_8E_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   component AND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
   
   component AND4B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
   
   component AND4B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
   
   component AND4B3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
   
begin
   I_36_30 : AND4
      port map (I0=>A2,
                I1=>A1,
                I2=>A0,
                I3=>E,
                O=>D7);
   
   I_36_31 : AND4B1
      port map (I0=>A0,
                I1=>A2,
                I2=>A1,
                I3=>E,
                O=>D6);
   
   I_36_32 : AND4B1
      port map (I0=>A1,
                I1=>A2,
                I2=>A0,
                I3=>E,
                O=>D5);
   
   I_36_33 : AND4B2
      port map (I0=>A1,
                I1=>A0,
                I2=>A2,
                I3=>E,
                O=>D4);
   
   I_36_34 : AND4B1
      port map (I0=>A2,
                I1=>A0,
                I2=>A1,
                I3=>E,
                O=>D3);
   
   I_36_35 : AND4B2
      port map (I0=>A2,
                I1=>A0,
                I2=>A1,
                I3=>E,
                O=>D2);
   
   I_36_36 : AND4B2
      port map (I0=>A2,
                I1=>A1,
                I2=>A0,
                I3=>E,
                O=>D1);
   
   I_36_37 : AND4B3
      port map (I0=>A2,
                I1=>A1,
                I2=>A0,
                I3=>E,
                O=>D0);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity FD8CE_MXILINX_CTLAB_SPI is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (7 downto 0); 
          Q   : out   std_logic_vector (7 downto 0));
end FD8CE_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of FD8CE_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(0),
                Q=>Q(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(1),
                Q=>Q(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(2),
                Q=>Q(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(3),
                Q=>Q(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(4),
                Q=>Q(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(5),
                Q=>Q(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(6),
                Q=>Q(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(7),
                Q=>Q(7));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR8CE_MXILINX_CTLAB_SPI is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (7 downto 0));
end SR8CE_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of SR8CE_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   signal Q_DUMMY : std_logic_vector (7 downto 0);
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   Q(7 downto 0) <= Q_DUMMY(7 downto 0);
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>SLI,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(0),
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(1),
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(2),
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(3),
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(4),
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(5),
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(6),
                Q=>Q_DUMMY(7));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI8REG_IN_MUSER_CTLAB_SPI is
   port ( SPI_CLK   : in    std_logic; 
          SPI_MOSI  : in    std_logic; 
          SPI_SSREG : in    std_logic; 
          REGSEL    : out   std_logic_vector (7 downto 0));
end SPI8REG_IN_MUSER_CTLAB_SPI;

architecture BEHAVIORAL of SPI8REG_IN_MUSER_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal XLXN_37   : std_logic_vector (7 downto 0);
   signal XLXN_38   : std_logic;
   signal XLXN_151  : std_logic;
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
   
   component SR8CE_MXILINX_CTLAB_SPI
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   component FD8CE_MXILINX_CTLAB_SPI
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (7 downto 0); 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   attribute HU_SET of XLXI_93 : label is "XLXI_93_92";
   attribute HU_SET of XLXI_94 : label is "XLXI_94_93";
begin
   XLXI_4 : GND
      port map (G=>XLXN_38);
   
   XLXI_85 : VCC
      port map (P=>XLXN_151);
   
   XLXI_93 : SR8CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLK,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                SLI=>SPI_MOSI,
                Q(7 downto 0)=>XLXN_37(7 downto 0));
   
   XLXI_94 : FD8CE_MXILINX_CTLAB_SPI
      port map (C=>SPI_SSREG,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                D(7 downto 0)=>XLXN_37(7 downto 0),
                Q(7 downto 0)=>REGSEL(7 downto 0));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M2_1E_MXILINX_CTLAB_SPI is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          E  : in    std_logic; 
          S0 : in    std_logic; 
          O  : out   std_logic);
end M2_1E_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of M2_1E_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   signal M0 : std_logic;
   signal M1 : std_logic;
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component AND3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
begin
   I_36_30 : AND3
      port map (I0=>D1,
                I1=>E,
                I2=>S0,
                O=>M1);
   
   I_36_31 : AND3B1
      port map (I0=>S0,
                I1=>E,
                I2=>D0,
                O=>M0);
   
   I_36_38 : OR2
      port map (I0=>M1,
                I1=>M0,
                O=>O);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M4_1E_MXILINX_CTLAB_SPI is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          D2 : in    std_logic; 
          D3 : in    std_logic; 
          E  : in    std_logic; 
          S0 : in    std_logic; 
          S1 : in    std_logic; 
          O  : out   std_logic);
end M4_1E_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of M4_1E_MXILINX_CTLAB_SPI is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal M01 : std_logic;
   signal M23 : std_logic;
   component M2_1E_MXILINX_CTLAB_SPI
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             E  : in    std_logic; 
             S0 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   component MUXF5
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             S  : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of MUXF5 : component is "BLACK_BOX";
   
   attribute HU_SET of I_M01 : label is "I_M01_95";
   attribute HU_SET of I_M23 : label is "I_M23_94";
begin
   I_M01 : M2_1E_MXILINX_CTLAB_SPI
      port map (D0=>D0,
                D1=>D1,
                E=>E,
                S0=>S0,
                O=>M01);
   
   I_M23 : M2_1E_MXILINX_CTLAB_SPI
      port map (D0=>D2,
                D1=>D3,
                E=>E,
                S0=>S0,
                O=>M23);
   
   I_O : MUXF5
      port map (I0=>M01,
                I1=>M23,
                S=>S1,
                O=>O);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity M2_1_MXILINX_CTLAB_SPI is
   port ( D0 : in    std_logic; 
          D1 : in    std_logic; 
          S0 : in    std_logic; 
          O  : out   std_logic);
end M2_1_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of M2_1_MXILINX_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   signal M0 : std_logic;
   signal M1 : std_logic;
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
begin
   I_36_7 : AND2B1
      port map (I0=>S0,
                I1=>D0,
                O=>M0);
   
   I_36_8 : OR2
      port map (I0=>M1,
                I1=>M0,
                O=>O);
   
   I_36_9 : AND2
      port map (I0=>D1,
                I1=>S0,
                O=>M1);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR16CLE_MXILINX_CTLAB_SPI is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (15 downto 0); 
          L   : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (15 downto 0));
end SR16CLE_MXILINX_CTLAB_SPI;

architecture BEHAVIORAL of SR16CLE_MXILINX_CTLAB_SPI is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal L_OR_CE : std_logic;
   signal MD0     : std_logic;
   signal MD1     : std_logic;
   signal MD2     : std_logic;
   signal MD3     : std_logic;
   signal MD4     : std_logic;
   signal MD5     : std_logic;
   signal MD6     : std_logic;
   signal MD7     : std_logic;
   signal MD8     : std_logic;
   signal MD9     : std_logic;
   signal MD10    : std_logic;
   signal MD11    : std_logic;
   signal MD12    : std_logic;
   signal MD13    : std_logic;
   signal MD14    : std_logic;
   signal MD15    : std_logic;
   signal Q_DUMMY : std_logic_vector (15 downto 0);
   component M2_1_MXILINX_CTLAB_SPI
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             S0 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   attribute HU_SET of I_MQ0 : label is "I_MQ0_96";
   attribute HU_SET of I_MQ1 : label is "I_MQ1_97";
   attribute HU_SET of I_MQ2 : label is "I_MQ2_98";
   attribute HU_SET of I_MQ3 : label is "I_MQ3_99";
   attribute HU_SET of I_MQ4 : label is "I_MQ4_111";
   attribute HU_SET of I_MQ5 : label is "I_MQ5_110";
   attribute HU_SET of I_MQ6 : label is "I_MQ6_109";
   attribute HU_SET of I_MQ7 : label is "I_MQ7_108";
   attribute HU_SET of I_MQ8 : label is "I_MQ8_100";
   attribute HU_SET of I_MQ9 : label is "I_MQ9_101";
   attribute HU_SET of I_MQ10 : label is "I_MQ10_103";
   attribute HU_SET of I_MQ11 : label is "I_MQ11_102";
   attribute HU_SET of I_MQ12 : label is "I_MQ12_107";
   attribute HU_SET of I_MQ13 : label is "I_MQ13_106";
   attribute HU_SET of I_MQ14 : label is "I_MQ14_104";
   attribute HU_SET of I_MQ15 : label is "I_MQ15_105";
begin
   Q(15 downto 0) <= Q_DUMMY(15 downto 0);
   I_MQ0 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>SLI,
                D1=>D(0),
                S0=>L,
                O=>MD0);
   
   I_MQ1 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(0),
                D1=>D(1),
                S0=>L,
                O=>MD1);
   
   I_MQ2 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(1),
                D1=>D(2),
                S0=>L,
                O=>MD2);
   
   I_MQ3 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(2),
                D1=>D(3),
                S0=>L,
                O=>MD3);
   
   I_MQ4 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(3),
                D1=>D(4),
                S0=>L,
                O=>MD4);
   
   I_MQ5 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(4),
                D1=>D(5),
                S0=>L,
                O=>MD5);
   
   I_MQ6 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(5),
                D1=>D(6),
                S0=>L,
                O=>MD6);
   
   I_MQ7 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(6),
                D1=>D(7),
                S0=>L,
                O=>MD7);
   
   I_MQ8 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(7),
                D1=>D(8),
                S0=>L,
                O=>MD8);
   
   I_MQ9 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(8),
                D1=>D(9),
                S0=>L,
                O=>MD9);
   
   I_MQ10 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(9),
                D1=>D(10),
                S0=>L,
                O=>MD10);
   
   I_MQ11 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(10),
                D1=>D(11),
                S0=>L,
                O=>MD11);
   
   I_MQ12 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(11),
                D1=>D(12),
                S0=>L,
                O=>MD12);
   
   I_MQ13 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(12),
                D1=>D(13),
                S0=>L,
                O=>MD13);
   
   I_MQ14 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(13),
                D1=>D(14),
                S0=>L,
                O=>MD14);
   
   I_MQ15 : M2_1_MXILINX_CTLAB_SPI
      port map (D0=>Q_DUMMY(14),
                D1=>D(15),
                S0=>L,
                O=>MD15);
   
   I_Q0 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD0,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD1,
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD2,
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD3,
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD4,
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD5,
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD6,
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD7,
                Q=>Q_DUMMY(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD8,
                Q=>Q_DUMMY(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD9,
                Q=>Q_DUMMY(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD10,
                Q=>Q_DUMMY(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD11,
                Q=>Q_DUMMY(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD12,
                Q=>Q_DUMMY(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD13,
                Q=>Q_DUMMY(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD14,
                Q=>Q_DUMMY(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>L_OR_CE,
                CLR=>CLR,
                D=>MD15,
                Q=>Q_DUMMY(15));
   
   I_36_67 : OR2
      port map (I0=>L,
                I1=>CE,
                O=>L_OR_CE);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI32_OUT_MUSER_CTLAB_SPI is
   port ( A0         : in    std_logic; 
          A1         : in    std_logic; 
          DATA0      : in    std_logic_vector (31 downto 0); 
          DATA1      : in    std_logic_vector (31 downto 0); 
          DATA2      : in    std_logic_vector (31 downto 0); 
          DATA3      : in    std_logic_vector (31 downto 0); 
          ENABLE     : in    std_logic; 
          SPI_CLK    : in    std_logic; 
          SPI_SSDATA : in    std_logic; 
          SPI_MISO   : out   std_logic);
end SPI32_OUT_MUSER_CTLAB_SPI;

architecture BEHAVIORAL of SPI32_OUT_MUSER_CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal Q0H                     : std_logic_vector (15 downto 0);
   signal Q0L                     : std_logic_vector (15 downto 0);
   signal Q1H                     : std_logic_vector (15 downto 0);
   signal Q1L                     : std_logic_vector (15 downto 0);
   signal Q2H                     : std_logic_vector (15 downto 0);
   signal Q2L                     : std_logic_vector (15 downto 0);
   signal Q3H                     : std_logic_vector (15 downto 0);
   signal Q3L                     : std_logic_vector (15 downto 0);
   signal SPI_CLKINV              : std_logic;
   signal SSDAT                   : std_logic;
   signal XLXN_244                : std_logic;
   signal XLXN_284                : std_logic;
   signal XLXN_291                : std_logic;
   signal XLXN_331                : std_logic;
   signal XLXI_205_SLI_openSignal : std_logic;
   signal XLXI_206_SLI_openSignal : std_logic;
   signal XLXI_208_SLI_openSignal : std_logic;
   signal XLXI_210_SLI_openSignal : std_logic;
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component FDC
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDC : component is "BLACK_BOX";
   
   component SR16CLE_MXILINX_CTLAB_SPI
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (15 downto 0); 
             L   : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component M4_1E_MXILINX_CTLAB_SPI
      port ( D0 : in    std_logic; 
             D1 : in    std_logic; 
             D2 : in    std_logic; 
             D3 : in    std_logic; 
             E  : in    std_logic; 
             S0 : in    std_logic; 
             S1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_203 : label is "XLXI_203_112";
   attribute HU_SET of XLXI_204 : label is "XLXI_204_113";
   attribute HU_SET of XLXI_205 : label is "XLXI_205_114";
   attribute HU_SET of XLXI_206 : label is "XLXI_206_115";
   attribute HU_SET of XLXI_208 : label is "XLXI_208_116";
   attribute HU_SET of XLXI_209 : label is "XLXI_209_117";
   attribute HU_SET of XLXI_210 : label is "XLXI_210_118";
   attribute HU_SET of XLXI_211 : label is "XLXI_211_119";
   attribute HU_SET of XLXI_212 : label is "XLXI_212_120";
begin
   XLXI_4 : GND
      port map (G=>XLXN_244);
   
   XLXI_119 : INV
      port map (I=>SPI_SSDATA,
                O=>SSDAT);
   
   XLXI_199 : FDC
      port map (C=>SPI_CLKINV,
                CLR=>SPI_SSDATA,
                D=>SSDAT,
                Q=>XLXN_284);
   
   XLXI_200 : INV
      port map (I=>XLXN_284,
                O=>XLXN_331);
   
   XLXI_203 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA0(31 downto 16),
                L=>XLXN_331,
                SLI=>Q0L(15),
                Q(15 downto 0)=>Q0H(15 downto 0));
   
   XLXI_204 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA1(31 downto 16),
                L=>XLXN_331,
                SLI=>Q1L(15),
                Q(15 downto 0)=>Q1H(15 downto 0));
   
   XLXI_205 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA0(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_205_SLI_openSignal,
                Q(15 downto 0)=>Q0L(15 downto 0));
   
   XLXI_206 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA1(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_206_SLI_openSignal,
                Q(15 downto 0)=>Q1L(15 downto 0));
   
   XLXI_207 : AND2
      port map (I0=>SSDAT,
                I1=>ENABLE,
                O=>XLXN_291);
   
   XLXI_208 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA2(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_208_SLI_openSignal,
                Q(15 downto 0)=>Q2L(15 downto 0));
   
   XLXI_209 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA2(31 downto 16),
                L=>XLXN_331,
                SLI=>Q2L(15),
                Q(15 downto 0)=>Q2H(15 downto 0));
   
   XLXI_210 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA3(15 downto 0),
                L=>XLXN_331,
                SLI=>XLXI_210_SLI_openSignal,
                Q(15 downto 0)=>Q3L(15 downto 0));
   
   XLXI_211 : SR16CLE_MXILINX_CTLAB_SPI
      port map (C=>SPI_CLKINV,
                CE=>SSDAT,
                CLR=>XLXN_244,
                D(15 downto 0)=>DATA3(31 downto 16),
                L=>XLXN_331,
                SLI=>Q3L(15),
                Q(15 downto 0)=>Q3H(15 downto 0));
   
   XLXI_212 : M4_1E_MXILINX_CTLAB_SPI
      port map (D0=>Q0H(15),
                D1=>Q1H(15),
                D2=>Q2H(15),
                D3=>Q3H(15),
                E=>XLXN_291,
                S0=>A0,
                S1=>A1,
                O=>SPI_MISO);
   
   XLXI_214 : INV
      port map (I=>SPI_CLK,
                O=>SPI_CLKINV);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity CTLAB_SPI is
   port ( MOSI  : in    std_logic; 
          SCK   : in    std_logic; 
          SPID0 : in    std_logic_vector (31 downto 0); 
          SPID1 : in    std_logic_vector (31 downto 0); 
          SPID2 : in    std_logic_vector (31 downto 0); 
          SPID3 : in    std_logic_vector (31 downto 0); 
          SSDAT : in    std_logic; 
          SSREG : in    std_logic; 
          MISO  : out   std_logic; 
          SPIQ0 : out   std_logic_vector (31 downto 0); 
          SPIQ1 : out   std_logic_vector (31 downto 0); 
          SPIQ2 : out   std_logic_vector (31 downto 0); 
          SPIQ3 : out   std_logic_vector (31 downto 0));
end CTLAB_SPI;

architecture BEHAVIORAL of CTLAB_SPI is
   attribute BOX_TYPE   : string ;
   attribute IOSTANDARD : string ;
   attribute SLEW       : string ;
   attribute DRIVE      : string ;
   attribute HU_SET     : string ;
   signal REGSEL   : std_logic_vector (7 downto 0);
   signal XLXN_139 : std_logic;
   signal XLXN_194 : std_logic;
   signal XLXN_197 : std_logic;
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
   
   component OBUFT
      port ( I : in    std_logic; 
             T : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute IOSTANDARD of OBUFT : component is "DEFAULT";
   attribute SLEW of OBUFT : component is "SLOW";
   attribute DRIVE of OBUFT : component is "12";
   attribute BOX_TYPE of OBUFT : component is "BLACK_BOX";
   
   component SPI32_OUT_MUSER_CTLAB_SPI
      port ( SPI_CLK    : in    std_logic; 
             SPI_SSDATA : in    std_logic; 
             A0         : in    std_logic; 
             A1         : in    std_logic; 
             ENABLE     : in    std_logic; 
             DATA0      : in    std_logic_vector (31 downto 0); 
             SPI_MISO   : out   std_logic; 
             DATA2      : in    std_logic_vector (31 downto 0); 
             DATA3      : in    std_logic_vector (31 downto 0); 
             DATA1      : in    std_logic_vector (31 downto 0));
   end component;
   
   component SPI8REG_IN_MUSER_CTLAB_SPI
      port ( SPI_MOSI  : in    std_logic; 
             SPI_CLK   : in    std_logic; 
             SPI_SSREG : in    std_logic; 
             REGSEL    : out   std_logic_vector (7 downto 0));
   end component;
   
   component SPI32_IN_MUSER_CTLAB_SPI
      port ( SPI_MOSI   : in    std_logic; 
             SPI_CLK    : in    std_logic; 
             DATA3      : out   std_logic_vector (31 downto 0); 
             DATA2      : out   std_logic_vector (31 downto 0); 
             DATA1      : out   std_logic_vector (31 downto 0); 
             DATA0      : out   std_logic_vector (31 downto 0); 
             SPI_SSDATA : in    std_logic; 
             A0         : in    std_logic; 
             A1         : in    std_logic; 
             ENABLE     : in    std_logic);
   end component;
   
   component D3_8E_MXILINX_CTLAB_SPI
      port ( A0 : in    std_logic; 
             A1 : in    std_logic; 
             A2 : in    std_logic; 
             E  : in    std_logic; 
             D0 : out   std_logic; 
             D1 : out   std_logic; 
             D2 : out   std_logic; 
             D3 : out   std_logic; 
             D4 : out   std_logic; 
             D5 : out   std_logic; 
             D6 : out   std_logic; 
             D7 : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_171 : label is "XLXI_171_121";
begin
   XLXI_6 : VCC
      port map (P=>XLXN_194);
   
   XLXI_44 : OBUFT
      port map (I=>XLXN_139,
                T=>SSDAT,
                O=>MISO);
   
   XLXI_110 : SPI32_OUT_MUSER_CTLAB_SPI
      port map (A0=>REGSEL(0),
                A1=>REGSEL(1),
                DATA0(31 downto 0)=>SPID0(31 downto 0),
                DATA1(31 downto 0)=>SPID1(31 downto 0),
                DATA2(31 downto 0)=>SPID2(31 downto 0),
                DATA3(31 downto 0)=>SPID3(31 downto 0),
                ENABLE=>XLXN_197,
                SPI_CLK=>SCK,
                SPI_SSDATA=>SSDAT,
                SPI_MISO=>XLXN_139);
   
   XLXI_168 : SPI8REG_IN_MUSER_CTLAB_SPI
      port map (SPI_CLK=>SCK,
                SPI_MOSI=>MOSI,
                SPI_SSREG=>SSREG,
                REGSEL(7 downto 0)=>REGSEL(7 downto 0));
   
   XLXI_169 : SPI32_IN_MUSER_CTLAB_SPI
      port map (A0=>REGSEL(0),
                A1=>REGSEL(1),
                ENABLE=>XLXN_197,
                SPI_CLK=>SCK,
                SPI_MOSI=>MOSI,
                SPI_SSDATA=>SSDAT,
                DATA0(31 downto 0)=>SPIQ0(31 downto 0),
                DATA1(31 downto 0)=>SPIQ1(31 downto 0),
                DATA2(31 downto 0)=>SPIQ2(31 downto 0),
                DATA3(31 downto 0)=>SPIQ3(31 downto 0));
   
   XLXI_171 : D3_8E_MXILINX_CTLAB_SPI
      port map (A0=>REGSEL(4),
                A1=>REGSEL(5),
                A2=>REGSEL(6),
                E=>XLXN_194,
                D0=>XLXN_197,
                D1=>open,
                D2=>open,
                D3=>open,
                D4=>open,
                D5=>open,
                D6=>open,
                D7=>open);
   
end BEHAVIORAL;