CTLAB_SPI Project Status (04/27/2016 - 14:12:53)
Project File:	Main.xise	Parser Errors:	No Errors
Module Name:	RasterScan	Implementation State:	Programming File Generated
Target Device:	xc3s400-4tq144	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	50 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	115	7,168	1%
Number of 4 input LUTs	102	7,168	1%
Number of occupied Slices	90	3,584	2%
Number of Slices containing only related logic	90	90	100%
Number of Slices containing unrelated logic	0	90	0%
Total Number of 4 input LUTs	152	7,168	2%
Number used as logic	102
Number used as a route-thru	50
Number of bonded IOBs	31	97	31%
Number of BUFGMUXs	3	8	37%
Average Fanout of Non-Clock Nets	2.80

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Mi 27. Apr 14:11:23 2016	0	47 Warnings (0 new)	4 Infos (0 new)
Translation Report	Current	Mi 27. Apr 14:12:09 2016	0	0	0
Map Report	Current	Mi 27. Apr 14:12:17 2016	0	1 Warning (0 new)	4 Infos (0 new)
Place and Route Report	Current	Mi 27. Apr 14:12:29 2016	0	2 Warnings (0 new)	2 Infos (1 new)
Power Report
Post-PAR Static Timing Report	Current	Mi 27. Apr 14:12:33 2016	0	0	6 Infos (0 new)
Bitgen Report	Current	Mi 27. Apr 14:12:46 2016	0	0	1 Info (0 new)

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Mi 27. Apr 14:12:47 2016
WebTalk Log File	Current	Mi 27. Apr 14:12:53 2016

Date Generated: 04/27/2016 - 14:12:53