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-- Company: 
-- Engineer: Carsten Meyer
-- 
-- Create Date:  17:17:17 04/27/2008 
-- Design Name: 
-- Module Name:  MPX10 - Behavioral 
-- Project Name: ct-Lab AsteroidsClock
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MPX18_OEWR is
    Port ( Q : out STD_LOGIC_VECTOR (18 downto 0);
           DA : in  STD_LOGIC_VECTOR (18 downto 0);
           DB : in  STD_LOGIC_VECTOR (18 downto 0);
           DAC : in  STD_LOGIC_VECTOR (0 to 7); -- Achtung: DAC ist MSB auf SRAM-Adr. 0!
			  OEAN : in STD_LOGIC;
			  WEBN : in STD_LOGIC;
			  OEN : out STD_LOGIC;
			  WEN : out STD_LOGIC;
			  DAENA : in STD_LOGIC;
			  DACLK : out STD_LOGIC;
           SEL : in  STD_LOGIC);
end MPX18_OEWR;

architecture behave of MPX18_OEWR is

begin
process(DA, DB, DAC, SEL, OEAN, WEBN, DAENA)
begin
if SEL='1' then -- AutoIncrement-Load durchschalten
      Q<=DB;
		OEN<='1';
		WEN<=WEBN;
		DACLK<='1';
   else
		if OEAN='0' then	-- Read Request von CPU-Core
			Q<=DA;
			OEN<='0';
			WEN<='1';
			DACLK<='0';
		else					-- falls OEAN inaktiv, DAC bedienen
			Q(7 downto 0)<=DAC;
			Q(18 downto 8)<=(others =>'0');
			OEN<='1';
			DACLK<= DAENA;
		end if;
   end if;
end process;
end behave;