--Design Name: TristateBus8
--Device: spartan3

library ieee;
use ieee.std_logic_1164.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity TristateBus8 is
  generic ( width : integer := 7 );
   port ( DIN  : in   std_logic_vector ( width downto 0); 
          DIS : in    std_ulogic; 
          DOUT : inout  std_logic_vector ( width downto 0)
			 );
end TristateBus8;


architecture rtl of TristateBus8 is
begin  --  rtl

  DOUT <= DIN when (DIS = '0') else
            (others => 'Z');

end rtl;