----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Carsten Meyer
-- 
-- Create Date:  17:17:17 04/27/2008 
-- Design Name: SRAM Interface für AutoIncrement-LoadCore
-- Module Name:  MPX18 - Behavioral 
-- Project Name: ct-Lab AsteroidsClock
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MPX18_OEWR is
  generic ( data_width : integer := 7 );
    Port ( 	ADDR : out STD_LOGIC_VECTOR (18 downto 0);
				P_ADDR : in  STD_LOGIC_VECTOR (18 downto 0);
				LC_ADDR : in  STD_LOGIC_VECTOR (18 downto 0);
				DAC : in  STD_LOGIC_VECTOR (7 downto 0); -- Achtung: DAC ist MSB auf SRAM-Adr. 0!
				P_OE : in STD_LOGIC;
				LC_WEN : in STD_LOGIC;
				OEN : out STD_LOGIC;
				WEN : out STD_LOGIC;
				DA_ENA : in STD_LOGIC;
				DA_CLK : out STD_LOGIC;
				LC_ENA : in  STD_LOGIC;
				LC_RAMD  : in   std_logic_vector ( 31 downto 0); 
				RDATA_Z : inout  std_logic_vector ( data_width downto 0)
			 );

end MPX18_OEWR;

architecture behave of MPX18_OEWR is

begin

RDATA_Z <= LC_RAMD(data_width downto 0) when (LC_ENA = '1') else (others => 'Z');

process(P_ADDR, LC_ADDR, DAC, LC_ENA, P_OE, LC_WEN, DA_ENA)
begin
	if LC_ENA='1' then -- AutoIncrement-Load durchschalten
      ADDR<=LC_ADDR;
		OEN<='1';
		WEN<=LC_WEN;
		DA_CLK<='0';
   else
		if P_OE='0' then	-- Read Request von CPU-Core
			ADDR<=P_ADDR;
			OEN<='0';
			WEN<='1';
			DA_CLK<='0';
		else					-- falls P_OE inaktiv, DAC bedienen
			ADDR(7)<=DAC(0);
			ADDR(6)<=DAC(1);
			ADDR(5)<=DAC(2);
			ADDR(4)<=DAC(3);
			ADDR(3)<=DAC(4);
			ADDR(2)<=DAC(5);
			ADDR(1)<=DAC(6);
			ADDR(0)<=DAC(7);
			ADDR(18 downto 8)<=(others =>'0');
			OEN<='1';
			DA_CLK<= DA_ENA;
		end if;
   end if;
end process;

end behave;