--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : ISE
--  /   /         Filename : COUNT_LC_tbw.ant
-- /___/   /\     Timestamp : Thu Feb 12 11:36:05 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: COUNT_LC_tbw
--Device: Xilinx
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE STD.TEXTIO.ALL;

ENTITY COUNT_LC_tbw IS
END COUNT_LC_tbw;

ARCHITECTURE testbench_arch OF COUNT_LC_tbw IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\ProjFPGA\ct-pacman\main\COUNT_LC_tbw.ano";

    COMPONENT COUNT_LC
        PORT (
            AdrCount : Out std_logic_vector (18 DownTo 0);
            SYSCLK : In std_logic;
            reset : In std_logic;
            incr_pulse : In std_logic;
            WEN : Out std_logic
        );
    END COMPONENT;

    SIGNAL AdrCount : std_logic_vector (18 DownTo 0) := "0000000000000000000";
    SIGNAL SYSCLK : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL incr_pulse : std_logic := '0';
    SIGNAL WEN : std_logic := '0';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 20 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 100 ns;

    BEGIN
        UUT : COUNT_LC
        PORT MAP (
            AdrCount => AdrCount,
            SYSCLK => SYSCLK,
            reset => reset,
            incr_pulse => incr_pulse,
            WEN => WEN
        );

        PROCESS    -- clock process for SYSCLK
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                SYSCLK <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                SYSCLK <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for SYSCLK
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_AdrCount(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", AdrCount, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, AdrCount);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_WEN(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", WEN, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, WEN);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_AdrCount(0);
            ANNOTATE_WEN(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 100;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 12 ns;
                TX_TIME := TX_TIME + 12;
                ANNOTATE_AdrCount(TX_TIME);
                ANNOTATE_WEN(TX_TIME);
                WAIT for 8 ns;
                TX_TIME := TX_TIME + 8;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  128ns
                WAIT FOR 128 ns;
                reset <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  188ns
                WAIT FOR 60 ns;
                reset <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  408ns
                WAIT FOR 220 ns;
                incr_pulse <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  448ns
                WAIT FOR 40 ns;
                incr_pulse <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  748ns
                WAIT FOR 300 ns;
                incr_pulse <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  788ns
                WAIT FOR 40 ns;
                incr_pulse <= '0';
                -- -------------------------------------
                WAIT FOR 232 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;