Logical network XLXI_183/XLXI_171/D1 has no load. The above info message is repeated 383 more times for the following (max. 5 shown): XLXI_183/XLXI_171/D2, XLXI_183/XLXI_171/D3, XLXI_183/XLXI_171/D4, XLXI_183/XLXI_171/D5, XLXI_183/XLXI_171/D6 To see the details of these info messages, please use the -detail switch. No environment variables are currently set. The following Virtex Blockram(s) is/are being retargeted to Virtex2 Blockram(s). This will waste 75% of Virtex2 Blockram capacity. To obtain better utilization, Please re-run memory generator to retarget to Virtex2 Blockram modules: RAMB4_S4 symbol "XLXI_11/rams/r0" (output signal=XLXI_11/ram_dout<3>), RAMB4_S4 symbol "XLXI_11/rams/r1" (output signal=XLXI_11/ram_dout<7>), RAMB4_S4 symbol "XLXI_11/vg/u_vector_ram_1/r0" (output signal=XLXI_11/vg/ram_dout_1<3>), RAMB4_S4 symbol "XLXI_11/vg/u_vector_ram_1/r1" (output signal=XLXI_11/vg/ram_dout_1<7>), RAMB4_S4 symbol "XLXI_11/vg/u_vector_ram_2/r0" (output signal=XLXI_11/vg/ram_dout_2<3>), RAMB4_S4 symbol "XLXI_11/vg/u_vector_ram_2/r1" (output signal=XLXI_11/vg/ram_dout_2<7>) All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_MPU4051/Clk/XLXI_21/I_Q0/Q_DUMMY_BUFG" (output signal=MPU4051/Clk) has a mix of clock and non-clock loads. The non-clock loads are: Pin I3 of XLXI_21/I_36_15 Pin I3 of XLXI_21/I_Q3/I_36_32 Pin I2 of XLXI_21/I_Q2/I_36_32 Pin I0 of XLXI_21/I_Q1/I_36_32 Pin D of MPU4051/tc01/T0_r_0 Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_XLXI_11/CLK_6/XLXI_21/I_Q2/Q_DUMMY_BUFG" (output signal=XLXI_11/CLK_6) has a mix of clock and non-clock loads. The non-clock loads are: Pin I1 of XLXI_21/I_36_15 Pin I1 of XLXI_21/I_Q3/I_36_32 The function generator MPU4051/core51/alu/ACC_Q<1>311 failed to merge with F5 multiplexer MPU4051/core51/alu/ACC_Q<4>134_SW1. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator MPU4051/core51/NPC_11_mux001347 failed to merge with F5 multiplexer MPU4051/core51/Stall_pipe270_SW6. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator XLXI_11/cpu/mcode/Mmux_Jump_mux0015_3 failed to merge with F5 multiplexer XLXI_11/cpu/mcode/Mmux_Jump_mux0008_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator XLXI_11/cpu/mcode/Mmux_Jump_mux0015_6 failed to merge with F5 multiplexer XLXI_11/cpu/mcode/Mmux_Jump_mux0008_5_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator MPU4051/core51/NPC_0_mux0013149_SW0 failed to merge with F5 multiplexer MPU4051/core51/NPC_0_mux001339_SW0. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator MPU4051/core51/SFR_RData<0>11 failed to merge with F5 multiplexer MPU4051/core51/SFR_RData<0>404_SW1. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator MPU4051/core51/alu/ACC_Q<0>31 failed to merge with F5 multiplexer MPU4051/core51/alu/ACC_Q<5>134_SW0_SW0. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator MPU4051/core51/NPC_1_mux0013149_SW0 failed to merge with F5 multiplexer MPU4051/core51/NPC_1_mux001339_SW0. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.