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-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 14.7
--  \   \         Application : sch2hdl
--  /   /         Filename : SPI8REG_IN.vhf
-- /___/   /\     Timestamp : 04/26/2016 12:07:00
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl E:/Dropbox/ct-AsteroidsClock/main/SPI8REG_IN.vhf -w E:/Dropbox/ct-AsteroidsClock/main/source/SPI8REG_IN.sch
--Design Name: SPI8REG_IN
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity FD8CE_MXILINX_SPI8REG_IN is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (7 downto 0); 
          Q   : out   std_logic_vector (7 downto 0));
end FD8CE_MXILINX_SPI8REG_IN;

architecture BEHAVIORAL of FD8CE_MXILINX_SPI8REG_IN is
   attribute BOX_TYPE   : string ;
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(0),
                Q=>Q(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(1),
                Q=>Q(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(2),
                Q=>Q(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(3),
                Q=>Q(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(4),
                Q=>Q(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(5),
                Q=>Q(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(6),
                Q=>Q(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(7),
                Q=>Q(7));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR8CE_MXILINX_SPI8REG_IN is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (7 downto 0));
end SR8CE_MXILINX_SPI8REG_IN;

architecture BEHAVIORAL of SR8CE_MXILINX_SPI8REG_IN is
   attribute BOX_TYPE   : string ;
   signal Q_DUMMY : std_logic_vector (7 downto 0);
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   Q(7 downto 0) <= Q_DUMMY(7 downto 0);
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>SLI,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(0),
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(1),
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(2),
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(3),
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(4),
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(5),
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(6),
                Q=>Q_DUMMY(7));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI8REG_IN is
   port ( SPI_CLK   : in    std_logic; 
          SPI_MOSI  : in    std_logic; 
          SPI_SSREG : in    std_logic; 
          REGSEL    : out   std_logic_vector (7 downto 0));
end SPI8REG_IN;

architecture BEHAVIORAL of SPI8REG_IN is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal XLXN_37   : std_logic_vector (7 downto 0);
   signal XLXN_38   : std_logic;
   signal XLXN_151  : std_logic;
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
   
   component SR8CE_MXILINX_SPI8REG_IN
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   component FD8CE_MXILINX_SPI8REG_IN
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (7 downto 0); 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   attribute HU_SET of XLXI_93 : label is "XLXI_93_64";
   attribute HU_SET of XLXI_94 : label is "XLXI_94_65";
begin
   XLXI_4 : GND
      port map (G=>XLXN_38);
   
   XLXI_85 : VCC
      port map (P=>XLXN_151);
   
   XLXI_93 : SR8CE_MXILINX_SPI8REG_IN
      port map (C=>SPI_CLK,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                SLI=>SPI_MOSI,
                Q(7 downto 0)=>XLXN_37(7 downto 0));
   
   XLXI_94 : FD8CE_MXILINX_SPI8REG_IN
      port map (C=>SPI_SSREG,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                D(7 downto 0)=>XLXN_37(7 downto 0),
                Q(7 downto 0)=>REGSEL(7 downto 0));
   
end BEHAVIORAL;