--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 14.7
--  \   \         Application : sch2hdl
--  /   /         Filename : SPI32_IN.vhf
-- /___/   /\     Timestamp : 04/26/2016 12:06:53
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl E:/Dropbox/ct-AsteroidsClock/main/SPI32_IN.vhf -w E:/Dropbox/ct-AsteroidsClock/main/source/SPI32_IN.sch
--Design Name: SPI32_IN
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity D2_4E_MXILINX_SPI32_IN is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic);
end D2_4E_MXILINX_SPI32_IN;

architecture BEHAVIORAL of D2_4E_MXILINX_SPI32_IN is
   attribute BOX_TYPE   : string ;
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component AND3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
   
   component AND3B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
   
begin
   I_36_30 : AND3
      port map (I0=>A1,
                I1=>A0,
                I2=>E,
                O=>D3);
   
   I_36_31 : AND3B1
      port map (I0=>A0,
                I1=>A1,
                I2=>E,
                O=>D2);
   
   I_36_32 : AND3B1
      port map (I0=>A1,
                I1=>A0,
                I2=>E,
                O=>D1);
   
   I_36_33 : AND3B2
      port map (I0=>A0,
                I1=>A1,
                I2=>E,
                O=>D0);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity FD16CE_MXILINX_SPI32_IN is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          D   : in    std_logic_vector (15 downto 0); 
          Q   : out   std_logic_vector (15 downto 0));
end FD16CE_MXILINX_SPI32_IN;

architecture BEHAVIORAL of FD16CE_MXILINX_SPI32_IN is
   attribute BOX_TYPE   : string ;
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(0),
                Q=>Q(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(1),
                Q=>Q(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(2),
                Q=>Q(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(3),
                Q=>Q(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(4),
                Q=>Q(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(5),
                Q=>Q(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(6),
                Q=>Q(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(7),
                Q=>Q(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(8),
                Q=>Q(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(9),
                Q=>Q(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(10),
                Q=>Q(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(11),
                Q=>Q(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(12),
                Q=>Q(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(13),
                Q=>Q(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(14),
                Q=>Q(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(15),
                Q=>Q(15));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SR16CE_MXILINX_SPI32_IN is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          SLI : in    std_logic; 
          Q   : out   std_logic_vector (15 downto 0));
end SR16CE_MXILINX_SPI32_IN;

architecture BEHAVIORAL of SR16CE_MXILINX_SPI32_IN is
   attribute BOX_TYPE   : string ;
   signal Q_DUMMY : std_logic_vector (15 downto 0);
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   Q(15 downto 0) <= Q_DUMMY(15 downto 0);
   I_Q0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>SLI,
                Q=>Q_DUMMY(0));
   
   I_Q1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(0),
                Q=>Q_DUMMY(1));
   
   I_Q2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(1),
                Q=>Q_DUMMY(2));
   
   I_Q3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(2),
                Q=>Q_DUMMY(3));
   
   I_Q4 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(3),
                Q=>Q_DUMMY(4));
   
   I_Q5 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(4),
                Q=>Q_DUMMY(5));
   
   I_Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(5),
                Q=>Q_DUMMY(6));
   
   I_Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(6),
                Q=>Q_DUMMY(7));
   
   I_Q8 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(7),
                Q=>Q_DUMMY(8));
   
   I_Q9 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(8),
                Q=>Q_DUMMY(9));
   
   I_Q10 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(9),
                Q=>Q_DUMMY(10));
   
   I_Q11 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(10),
                Q=>Q_DUMMY(11));
   
   I_Q12 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(11),
                Q=>Q_DUMMY(12));
   
   I_Q13 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(12),
                Q=>Q_DUMMY(13));
   
   I_Q14 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(13),
                Q=>Q_DUMMY(14));
   
   I_Q15 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(14),
                Q=>Q_DUMMY(15));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SPI32_IN is
   port ( A0         : in    std_logic; 
          A1         : in    std_logic; 
          ENABLE     : in    std_logic; 
          SPI_CLK    : in    std_logic; 
          SPI_MOSI   : in    std_logic; 
          SPI_SSDATA : in    std_logic; 
          DATA0      : out   std_logic_vector (31 downto 0); 
          DATA1      : out   std_logic_vector (31 downto 0); 
          DATA2      : out   std_logic_vector (31 downto 0); 
          DATA3      : out   std_logic_vector (31 downto 0));
end SPI32_IN;

architecture BEHAVIORAL of SPI32_IN is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal Sel0       : std_logic;
   signal Sel1       : std_logic;
   signal Sel2       : std_logic;
   signal Sel3       : std_logic;
   signal ShiftLSB   : std_logic_vector (15 downto 0);
   signal ShiftMSB   : std_logic_vector (15 downto 0);
   signal XLXN_38    : std_logic;
   signal XLXN_130   : std_logic;
   signal XLXN_151   : std_logic;
   component SR16CE_MXILINX_SPI32_IN
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             SLI : in    std_logic; 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
   
   component FD16CE_MXILINX_SPI32_IN
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (15 downto 0); 
             Q   : out   std_logic_vector (15 downto 0));
   end component;
   
   component D2_4E_MXILINX_SPI32_IN
      port ( A0 : in    std_logic; 
             A1 : in    std_logic; 
             E  : in    std_logic; 
             D0 : out   std_logic; 
             D1 : out   std_logic; 
             D2 : out   std_logic; 
             D3 : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_2 : label is "XLXI_2_0";
   attribute HU_SET of XLXI_3 : label is "XLXI_3_1";
   attribute HU_SET of XLXI_88 : label is "XLXI_88_2";
   attribute HU_SET of XLXI_89 : label is "XLXI_89_3";
   attribute HU_SET of XLXI_96 : label is "XLXI_96_10";
   attribute HU_SET of XLXI_100 : label is "XLXI_100_4";
   attribute HU_SET of XLXI_101 : label is "XLXI_101_5";
   attribute HU_SET of XLXI_102 : label is "XLXI_102_6";
   attribute HU_SET of XLXI_103 : label is "XLXI_103_7";
   attribute HU_SET of XLXI_104 : label is "XLXI_104_8";
   attribute HU_SET of XLXI_105 : label is "XLXI_105_9";
begin
   XLXI_2 : SR16CE_MXILINX_SPI32_IN
      port map (C=>SPI_CLK,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                SLI=>SPI_MOSI,
                Q(15 downto 0)=>ShiftLSB(15 downto 0));
   
   XLXI_3 : SR16CE_MXILINX_SPI32_IN
      port map (C=>SPI_CLK,
                CE=>XLXN_151,
                CLR=>XLXN_38,
                SLI=>ShiftLSB(15),
                Q(15 downto 0)=>ShiftMSB(15 downto 0));
   
   XLXI_4 : GND
      port map (G=>XLXN_38);
   
   XLXI_85 : VCC
      port map (P=>XLXN_151);
   
   XLXI_88 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel0,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA0(15 downto 0));
   
   XLXI_89 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel0,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA0(31 downto 16));
   
   XLXI_96 : D2_4E_MXILINX_SPI32_IN
      port map (A0=>A0,
                A1=>A1,
                E=>ENABLE,
                D0=>Sel0,
                D1=>Sel1,
                D2=>Sel2,
                D3=>Sel3);
   
   XLXI_100 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel1,
                CLR=>XLXN_130,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA1(15 downto 0));
   
   XLXI_101 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel1,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA1(31 downto 16));
   
   XLXI_102 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel2,
                CLR=>XLXN_130,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA2(15 downto 0));
   
   XLXI_103 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel2,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA2(31 downto 16));
   
   XLXI_104 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel3,
                CLR=>XLXN_130,
                D(15 downto 0)=>ShiftLSB(15 downto 0),
                Q(15 downto 0)=>DATA3(15 downto 0));
   
   XLXI_105 : FD16CE_MXILINX_SPI32_IN
      port map (C=>SPI_SSDATA,
                CE=>Sel3,
                CLR=>XLXN_38,
                D(15 downto 0)=>ShiftMSB(15 downto 0),
                Q(15 downto 0)=>DATA3(31 downto 16));
   
end BEHAVIORAL;