Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s400
Project ID (random number) 4e1efdf5e9aa4373aadfd4b1929c877c.5A4CD53EDB914E4F8C287B80FCD973BF.9 Target Package: tq144
Registration ID 174235926_0_0_175 Target Speed: -4
Date Generated 2016-04-26T15:16:31 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name AMD Phenom(tm) 8750 Triple-Core Processor CPU Speed 2400 MHz
CPU Name AMD Phenom(tm) 8750 Triple-Core Processor CPU Speed 2400 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=2
  • 4-bit up accumulator=1
  • 8-bit up loadable accumulator=1
 Adders/Subtractors=61
  • 13-bit adder=2
  • 16-bit adder=12
  • 16-bit addsub=1
  • 16-bit subtractor=1
  • 2-bit adder=1
  • 2-bit adder carry in=1
  • 20-bit adder=1
  • 4-bit adder=3
  • 4-bit adder carry in=1
  • 4-bit subtractor=2
  • 5-bit adder=3
  • 5-bit adder carry in=1
  • 6-bit adder=5
  • 6-bit subtractor=2
  • 7-bit adder=3
  • 7-bit subtractor=1
  • 8-bit adder=8
  • 8-bit addsub=2
  • 8-bit subtractor=4
  • 9-bit adder=6
  • 9-bit subtractor=1
 Comparators=17
  • 2-bit comparator equal=1
  • 3-bit comparator equal=1
  • 3-bit comparator not equal=1
  • 4-bit comparator greatequal=1
  • 4-bit comparator greater=2
  • 5-bit comparator greater=2
  • 8-bit comparator equal=4
  • 8-bit comparator less=1
  • 8-bit comparator not equal=4
 Counters=27
  • 10-bit up counter=1
  • 11-bit up counter=1
  • 12-bit up counter=2
  • 12-bit updown counter=2
  • 2-bit up counter=1
  • 3-bit up counter=2
  • 4-bit up counter=8
  • 5-bit down counter=1
  • 5-bit up counter=1
  • 6-bit down counter=1
  • 7-bit down counter=1
  • 8-bit down counter=4
  • 8-bit up counter=2
 Decoders=1
  • 1-of-4 decoder=1
 FSMs=1 Multiplexers=58
  • 1-bit 4-to-1 multiplexer=24
  • 1-bit 6-to-1 multiplexer=8
  • 1-bit 8-to-1 multiplexer=11
  • 2-bit 32-to-1 multiplexer=1
  • 2-bit 8-to-1 multiplexer=5
  • 24-bit 4-to-1 multiplexer=1
  • 3-bit 4-to-1 multiplexer=6
  • 4-bit 16-to-1 multiplexer=1
  • 8-bit 4-to-1 multiplexer=1
 Multipliers=1
  • 8x8-bit multiplier=1
 RAMs=2
  • 256x8-bit dual-port distributed RAM=2
 ROMs=7
  • 16x10-bit ROM=1
  • 256x4-bit ROM=1
  • 4x1-bit ROM=2
  • 4x13-bit ROM=1
  • 4x2-bit ROM=2
 Registers=1458
  • Flip-Flops=1458
 Xors=21
  • 1-bit xor2=13
  • 1-bit xor3=2
  • 1-bit xor4=1
  • 1-bit xor8=1
  • 8-bit xor2=4
 		MiscellaneousStatistics
  • AGG_BONDED_IO=32
  • AGG_IO=32
  • AGG_SLICE=2838
  • NUM_4_INPUT_LUT=4896
  • NUM_BONDED_IOB=32
  • NUM_BUFGMUX=7
  • NUM_CYMUX=430
  • NUM_DP_RAM=512
  • NUM_LUT_RT=217
  • NUM_MULT18X18=1
  • NUM_MULTAND=8
  • NUM_RAMB16=14
  • NUM_RPM=5
  • NUM_SHIFT=14
  • NUM_SLICEL=2539
  • NUM_SLICEM=299
  • NUM_SLICE_FF=1283
  • NUM_XOR=432
 		NetStatistics
  • NumNets_Active=5215
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=150
  • NumNodesOfType_Active_BRAMDUMMY=40
  • NumNodesOfType_Active_CLKPIN=1149
  • NumNodesOfType_Active_CNTRLPIN=1281
  • NumNodesOfType_Active_DOUBLE=19287
  • NumNodesOfType_Active_DUMMY=16653
  • NumNodesOfType_Active_DUMMYESC=6
  • NumNodesOfType_Active_GLOBAL=361
  • NumNodesOfType_Active_HFULLHEX=320
  • NumNodesOfType_Active_HLONG=71
  • NumNodesOfType_Active_HUNIHEX=2011
  • NumNodesOfType_Active_INPUT=18318
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OMUX=5131
  • NumNodesOfType_Active_OUTPUT=5183
  • NumNodesOfType_Active_PREBXBY=1295
  • NumNodesOfType_Active_VFULLHEX=956
  • NumNodesOfType_Active_VLONG=155
  • NumNodesOfType_Active_VUNIHEX=1261
  • NumNodesOfType_Vcc_CNTRLPIN=23
  • NumNodesOfType_Vcc_DUMMY=15
  • NumNodesOfType_Vcc_INPUT=78
  • NumNodesOfType_Vcc_PREBXBY=60
  • NumNodesOfType_Vcc_VCCOUT=82
 SiteStatistics
  • IOB-DIFFM=15
  • IOB-DIFFS=16
  • SLICEL-SLICEM=1156
 		SiteSummary
  • BUFGMUX=7
  • BUFGMUX_GCLKMUX=7
  • BUFGMUX_GCLK_BUFFER=7
  • IOB=32
  • IOB_INBUF=6
  • IOB_OUTBUF=26
  • IOB_PAD=32
  • MULT18X18=1
  • MULT18X18_BLACKBOX=1
  • RAMB16=14
  • RAMB16_RAMB16=14
  • RAMB16_RAMB16A=14
  • SLICEL=2539
  • SLICEL_C1VDD=44
  • SLICEL_C2VDD=23
  • SLICEL_CYMUXF=231
  • SLICEL_CYMUXG=199
  • SLICEL_F=2174
  • SLICEL_F5MUX=426
  • SLICEL_F6MUX=29
  • SLICEL_FAND=5
  • SLICEL_FFX=665
  • SLICEL_FFY=600
  • SLICEL_G=2129
  • SLICEL_GAND=3
  • SLICEL_GNDF=101
  • SLICEL_GNDG=99
  • SLICEL_XORF=219
  • SLICEL_XORG=213
  • SLICEM=299
  • SLICEM_F=294
  • SLICEM_F5MUX=32
  • SLICEM_F6MUX=32
  • SLICEM_FFX=7
  • SLICEM_FFY=11
  • SLICEM_G=299
  • SLICEM_WSGEN=267
 
Configuration Data
BUFGMUX
  • S=[S_INV:7] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:7]
  • S=[S_INV:7] [S:0]
 IOB
  • O1=[O1_INV:10] [O1:16]
  • T1=[T1_INV:0] [T1:1]
 IOB_OUTBUF
  • IN=[IN_INV:10] [IN:16]
  • TRI=[TRI_INV:0] [TRI:1]
 IOB_PAD
  • DRIVEATTRBOX=[12:26]
  • IOATTRBOX=[LVTTL:32]
  • PULL=[PULLUP:1]
  • SLEW=[SLOW:26]
 RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:14]
  • ENA=[ENA_INV:0] [ENA:14]
  • SSRA=[SSRA_INV:0] [SSRA:14]
  • WEA=[WEA:14] [WEA_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:14]
  • ENA=[ENA_INV:0] [ENA:14]
  • PORTA_ATTR=[2048X9:6] [4096X4:8]
  • SSRA=[SSRA_INV:0] [SSRA:14]
  • WEA=[WEA:14] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:14]
 SLICEL
  • BX=[BX_INV:12] [BX:678]
  • BY=[BY:349] [BY_INV:16]
  • CE=[CE:608] [CE_INV:8]
  • CIN=[CIN_INV:0] [CIN:193]
  • CLK=[CLK:852] [CLK_INV:16]
  • SR=[SR:111] [SR_INV:123]
 SLICEL_CYMUXF
  • 0=[0:231] [0_INV:0]
  • 1=[1_INV:0] [1:231]
 SLICEL_CYMUXG
  • 0=[0:199] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:426] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:29] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:512] [CE_INV:7]
  • CK=[CK:651] [CK_INV:14]
  • D=[D:653] [D_INV:12]
  • FFX_INIT_ATTR=[INIT0:633] [INIT1:32]
  • FFX_SR_ATTR=[SRLOW:648] [SRHIGH:17]
  • LATCH_OR_FF=[FF:665]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:42] [SR_INV:107]
  • SYNC_ATTR=[ASYNC:623] [SYNC:42]
 SLICEL_FFY
  • CE=[CE:393] [CE_INV:8]
  • CK=[CK:584] [CK_INV:16]
  • D=[D:584] [D_INV:16]
  • FFY_INIT_ATTR=[INIT0:574] [INIT1:26]
  • FFY_SR_ATTR=[SRLOW:588] [SRHIGH:12]
  • LATCH_OR_FF=[FF:600]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:97] [SR_INV:54]
  • SYNC_ATTR=[ASYNC:503] [SYNC:97]
 SLICEL_XORF
  • 1=[1_INV:0] [1:219]
 SLICEM
  • BX=[BX_INV:0] [BX:36]
  • BY=[BY:299] [BY_INV:0]
  • CE=[CE:9] [CE_INV:0]
  • CLK=[CLK:267] [CLK_INV:0]
  • SR=[SR:267] [SR_INV:0]
 SLICEM_F
  • DI=[DI:259] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:256] [SHIFT_REG:3]
  • LUT_OR_MEM=[LUT:35] [RAM:259]
 SLICEM_F5MUX
  • S0=[S0:32] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:32] [S0_INV:0]
 SLICEM_FFX
  • CE=[CE:5] [CE_INV:0]
  • CK=[CK:7] [CK_INV:0]
  • D=[D:7] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:7]
  • FFX_SR_ATTR=[SRLOW:7]
  • LATCH_OR_FF=[FF:7]
  • SYNC_ATTR=[ASYNC:7]
 SLICEM_FFY
  • CE=[CE:9] [CE_INV:0]
  • CK=[CK:11] [CK_INV:0]
  • D=[D:11] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:11]
  • FFY_SR_ATTR=[SRLOW:11]
  • LATCH_OR_FF=[FF:11]
  • SYNC_ATTR=[ASYNC:11]
 SLICEM_G
  • DI=[DI:267] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:256] [SHIFT_REG:11]
  • LUT_OR_MEM=[LUT:32] [RAM:267]
 SLICEM_WSGEN
  • CK=[CK:267] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:11]
  • WE=[WE_INV:0] [WE:267]
 
Pin Data
BUFGMUX
  • I0=7
  • O=7
  • S=7
 BUFGMUX_GCLKMUX
  • I0=7
  • OUT=7
  • S=7
 BUFGMUX_GCLK_BUFFER
  • IN=7
  • OUT=7
 IOB
  • I=6
  • O1=26
  • PAD=32
  • T1=1
 IOB_INBUF
  • IN=6
  • OUT=6
 IOB_OUTBUF
  • IN=26
  • OUT=26
  • TRI=1
 IOB_PAD
  • PAD=32
 MULT18X18
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • P0=1
  • P1=1
  • P10=1
  • P11=1
  • P12=1
  • P13=1
  • P14=1
  • P15=1
  • P2=1
  • P3=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
 MULT18X18_BLACKBOX
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • P0=1
  • P1=1
  • P10=1
  • P11=1
  • P12=1
  • P13=1
  • P14=1
  • P15=1
  • P2=1
  • P3=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
 RAMB16
  • ADDRA10=14
  • ADDRA11=14
  • ADDRA12=14
  • ADDRA13=14
  • ADDRA2=8
  • ADDRA3=14
  • ADDRA4=14
  • ADDRA5=14
  • ADDRA6=14
  • ADDRA7=14
  • ADDRA8=14
  • ADDRA9=14
  • CLKA=14
  • DIA0=6
  • DIA1=6
  • DIA2=6
  • DIA3=6
  • DOA0=14
  • DOA1=14
  • DOA2=14
  • DOA3=14
  • DOA4=6
  • DOA5=6
  • DOA6=6
  • DOA7=6
  • ENA=14
  • SSRA=14
  • WEA=14
 RAMB16_RAMB16
  • ADDRA=14
  • DIA=14
  • DOA=14
 RAMB16_RAMB16A
  • ADDRA=14
  • ADDRA10=14
  • ADDRA11=14
  • ADDRA12=14
  • ADDRA13=14
  • ADDRA2=8
  • ADDRA3=14
  • ADDRA4=14
  • ADDRA5=14
  • ADDRA6=14
  • ADDRA7=14
  • ADDRA8=14
  • ADDRA9=14
  • CLKA=14
  • DIA=14
  • DIA0=6
  • DIA1=6
  • DIA2=6
  • DIA3=6
  • DOA=14
  • DOA0=14
  • DOA1=14
  • DOA2=14
  • DOA3=14
  • DOA4=6
  • DOA5=6
  • DOA6=6
  • DOA7=6
  • ENA=14
  • SSRA=14
  • WEA=14
 SLICEL
  • BX=690
  • BY=365
  • CE=616
  • CIN=193
  • CLK=868
  • COUT=199
  • F1=2161
  • F2=2033
  • F3=1802
  • F4=1325
  • F5=58
  • FX=16
  • FXINA=29
  • FXINB=29
  • G1=2089
  • G2=1973
  • G3=1749
  • G4=1260
  • SR=234
  • X=1715
  • XB=5
  • XQ=665
  • Y=1478
  • YQ=600
 SLICEL_C1VDD
  • 1=44
 SLICEL_C2VDD
  • 1=23
 SLICEL_CYMUXF
  • 0=231
  • 1=231
  • OUT=231
  • S0=231
 SLICEL_CYMUXG
  • 0=199
  • 1=199
  • OUT=199
  • S0=199
 SLICEL_F
  • A1=2161
  • A2=2033
  • A3=1802
  • A4=1325
  • D=2174
 SLICEL_F5MUX
  • F=426
  • G=426
  • OUT=426
  • S0=426
 SLICEL_F6MUX
  • 0=29
  • 1=29
  • OUT=29
  • S0=29
 SLICEL_FAND
  • 0=5
  • 1=5
  • O=5
 SLICEL_FFX
  • CE=519
  • CK=665
  • D=665
  • Q=665
  • REV=1
  • SR=149
 SLICEL_FFY
  • CE=401
  • CK=600
  • D=600
  • Q=600
  • REV=1
  • SR=151
 SLICEL_G
  • A1=2089
  • A2=1973
  • A3=1749
  • A4=1260
  • D=2129
 SLICEL_GAND
  • 0=3
  • 1=3
  • O=3
 SLICEL_GNDF
  • 0=101
 SLICEL_GNDG
  • 0=99
 SLICEL_XORF
  • 0=219
  • 1=219
  • O=219
 SLICEL_XORG
  • 0=213
  • 1=213
  • O=213
 SLICEM
  • BX=36
  • BY=299
  • CE=9
  • CLK=267
  • F1=294
  • F2=294
  • F3=292
  • F4=260
  • F5=32
  • FX=16
  • FXINA=32
  • FXINB=32
  • G1=299
  • G2=299
  • G3=299
  • G4=267
  • SR=267
  • X=256
  • XQ=7
  • Y=16
  • YQ=11
 SLICEM_F
  • A1=294
  • A2=294
  • A3=292
  • A4=260
  • D=294
  • DI=259
  • WF1=256
  • WF2=256
  • WF3=256
  • WF4=256
  • WS=259
 SLICEM_F5MUX
  • F=32
  • G=32
  • OUT=32
  • S0=32
 SLICEM_F6MUX
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
 SLICEM_FFX
  • CE=5
  • CK=7
  • D=7
  • Q=7
 SLICEM_FFY
  • CE=9
  • CK=11
  • D=11
  • Q=11
 SLICEM_G
  • A1=299
  • A2=299
  • A3=299
  • A4=267
  • D=43
  • DI=267
  • WG1=256
  • WG2=256
  • WG3=256
  • WG4=256
  • WS=267
 SLICEM_WSGEN
  • CK=267
  • WE=267
  • WSF=259
  • WSG=267
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 11 9 0 0 0 0 0
bitgen 17 17 0 0 0 0 0
map 22 20 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 24 24 0 0 0 0 0
par 20 18 0 0 0 0 0
trce 17 17 0 0 0 0 0
xst 91 89 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=Schematic
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-04-22T11:17:28 PROP_intWbtProjectID=5A4CD53EDB914E4F8C287B80FCD973BF
PROP_intWbtProjectIteration=9 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s400 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=VHDL
FILE_SCHEMATIC=5 FILE_UCF=1
FILE_VHDL=32
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=134 NGDBUILD_NUM_AND2B1=130 NGDBUILD_NUM_AND3=5 NGDBUILD_NUM_AND3B1=4
NGDBUILD_NUM_AND3B2=1 NGDBUILD_NUM_AND4=3 NGDBUILD_NUM_AND4B1=3 NGDBUILD_NUM_AND4B2=3
NGDBUILD_NUM_AND4B3=1 NGDBUILD_NUM_AND5=1 NGDBUILD_NUM_BUF=11 NGDBUILD_NUM_BUFG=4
NGDBUILD_NUM_BUFGP=3 NGDBUILD_NUM_FD=79 NGDBUILD_NUM_FDC=116 NGDBUILD_NUM_FDCE=739
NGDBUILD_NUM_FDE=398 NGDBUILD_NUM_FDP=8 NGDBUILD_NUM_FDPE=30 NGDBUILD_NUM_FDR=61
NGDBUILD_NUM_FDRE=56 NGDBUILD_NUM_FDRS=2 NGDBUILD_NUM_FDS=18 NGDBUILD_NUM_FDSE=2
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=72 NGDBUILD_NUM_LUT1=206
NGDBUILD_NUM_LUT2=381 NGDBUILD_NUM_LUT2_D=27 NGDBUILD_NUM_LUT2_L=18 NGDBUILD_NUM_LUT3=927
NGDBUILD_NUM_LUT3_D=70 NGDBUILD_NUM_LUT3_L=30 NGDBUILD_NUM_LUT4=2164 NGDBUILD_NUM_LUT4_D=188
NGDBUILD_NUM_LUT4_L=229 NGDBUILD_NUM_MULT18X18=1 NGDBUILD_NUM_MULT_AND=8 NGDBUILD_NUM_MUXCY=430
NGDBUILD_NUM_MUXF5=458 NGDBUILD_NUM_MUXF6=45 NGDBUILD_NUM_MUXF7=16 NGDBUILD_NUM_OBUF=25
NGDBUILD_NUM_OBUFT=1 NGDBUILD_NUM_OR2=140 NGDBUILD_NUM_PULLUP=1 NGDBUILD_NUM_RAM16X1D=256
NGDBUILD_NUM_RAMB4_S4=6 NGDBUILD_NUM_SRL16=2 NGDBUILD_NUM_SRLC16E=12 NGDBUILD_NUM_VCC=2
NGDBUILD_NUM_XOR2=8 NGDBUILD_NUM_XORCY=432
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=134 NGDBUILD_NUM_AND2B1=130 NGDBUILD_NUM_AND3=5 NGDBUILD_NUM_AND3B1=4
NGDBUILD_NUM_AND3B2=1 NGDBUILD_NUM_AND4=3 NGDBUILD_NUM_AND4B1=3 NGDBUILD_NUM_AND4B2=3
NGDBUILD_NUM_AND4B3=1 NGDBUILD_NUM_AND5=1 NGDBUILD_NUM_BUF=11 NGDBUILD_NUM_BUFG=7
NGDBUILD_NUM_FD=79 NGDBUILD_NUM_FDC=116 NGDBUILD_NUM_FDCE=739 NGDBUILD_NUM_FDE=398
NGDBUILD_NUM_FDP=8 NGDBUILD_NUM_FDPE=30 NGDBUILD_NUM_FDR=61 NGDBUILD_NUM_FDRE=56
NGDBUILD_NUM_FDRS=2 NGDBUILD_NUM_FDS=18 NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=3 NGDBUILD_NUM_INV=72 NGDBUILD_NUM_LUT1=206
NGDBUILD_NUM_LUT2=381 NGDBUILD_NUM_LUT2_D=27 NGDBUILD_NUM_LUT2_L=18 NGDBUILD_NUM_LUT3=927
NGDBUILD_NUM_LUT3_D=70 NGDBUILD_NUM_LUT3_L=30 NGDBUILD_NUM_LUT4=2164 NGDBUILD_NUM_LUT4_D=188
NGDBUILD_NUM_LUT4_L=229 NGDBUILD_NUM_MULT18X18=1 NGDBUILD_NUM_MULT_AND=8 NGDBUILD_NUM_MUXCY=430
NGDBUILD_NUM_MUXF5=458 NGDBUILD_NUM_MUXF6=45 NGDBUILD_NUM_MUXF7=16 NGDBUILD_NUM_OBUF=25
NGDBUILD_NUM_OBUFT=1 NGDBUILD_NUM_OR2=140 NGDBUILD_NUM_PULLUP=1 NGDBUILD_NUM_RAMB16_S4=2
NGDBUILD_NUM_RAMB16_S9=6 NGDBUILD_NUM_RAMB4_S4=6 NGDBUILD_NUM_SRLC16E=14 NGDBUILD_NUM_VCC=2
NGDBUILD_NUM_XOR2=8 NGDBUILD_NUM_XORCY=432
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5